1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from XBar import L2XBar
51from InstTracer import InstTracer
52from CPUTracers import ExeTracer
53from MemObject import MemObject
54from ClockDomain import *
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59 from AlphaTLB import AlphaDTB, AlphaITB
60 from AlphaInterrupts import AlphaInterrupts
61 from AlphaISA import AlphaISA
62 isa_class = AlphaISA
63elif buildEnv['TARGET_ISA'] == 'sparc':
64 from SparcTLB import SparcTLB
65 from SparcInterrupts import SparcInterrupts
66 from SparcISA import SparcISA
67 isa_class = SparcISA
68elif buildEnv['TARGET_ISA'] == 'x86':
69 from X86TLB import X86TLB
70 from X86LocalApic import X86LocalApic
71 from X86ISA import X86ISA
72 isa_class = X86ISA
73elif buildEnv['TARGET_ISA'] == 'mips':
74 from MipsTLB import MipsTLB
75 from MipsInterrupts import MipsInterrupts
76 from MipsISA import MipsISA
77 isa_class = MipsISA
78elif buildEnv['TARGET_ISA'] == 'arm':
79 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
80 from ArmInterrupts import ArmInterrupts
81 from ArmISA import ArmISA
82 isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84 from PowerTLB import PowerTLB
85 from PowerInterrupts import PowerInterrupts
86 from PowerISA import PowerISA
87 isa_class = PowerISA
| 1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.defines import buildEnv
47from m5.params import *
48from m5.proxy import *
49
50from XBar import L2XBar
51from InstTracer import InstTracer
52from CPUTracers import ExeTracer
53from MemObject import MemObject
54from ClockDomain import *
55
56default_tracer = ExeTracer()
57
58if buildEnv['TARGET_ISA'] == 'alpha':
59 from AlphaTLB import AlphaDTB, AlphaITB
60 from AlphaInterrupts import AlphaInterrupts
61 from AlphaISA import AlphaISA
62 isa_class = AlphaISA
63elif buildEnv['TARGET_ISA'] == 'sparc':
64 from SparcTLB import SparcTLB
65 from SparcInterrupts import SparcInterrupts
66 from SparcISA import SparcISA
67 isa_class = SparcISA
68elif buildEnv['TARGET_ISA'] == 'x86':
69 from X86TLB import X86TLB
70 from X86LocalApic import X86LocalApic
71 from X86ISA import X86ISA
72 isa_class = X86ISA
73elif buildEnv['TARGET_ISA'] == 'mips':
74 from MipsTLB import MipsTLB
75 from MipsInterrupts import MipsInterrupts
76 from MipsISA import MipsISA
77 isa_class = MipsISA
78elif buildEnv['TARGET_ISA'] == 'arm':
79 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
80 from ArmInterrupts import ArmInterrupts
81 from ArmISA import ArmISA
82 isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84 from PowerTLB import PowerTLB
85 from PowerInterrupts import PowerInterrupts
86 from PowerISA import PowerISA
87 isa_class = PowerISA
|
| 88elif buildEnv['TARGET_ISA'] == 'riscv':
89 from RiscvTLB import RiscvTLB
90 from RiscvInterrupts import RiscvInterrupts
91 from RiscvISA import RiscvISA
92 isa_class = RiscvISA
|
88
89class BaseCPU(MemObject):
90 type = 'BaseCPU'
91 abstract = True
92 cxx_header = "cpu/base.hh"
93
94 @classmethod
95 def export_methods(cls, code):
96 code('''
97 void switchOut();
98 void takeOverFrom(BaseCPU *cpu);
99 bool switchedOut();
100 void flushTLBs();
101 Counter totalInsts();
102 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
103 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
104 uint64_t getCurrentInstCount(ThreadID tid);
105''')
106
107 @classmethod
108 def memory_mode(cls):
109 """Which memory mode does this CPU require?"""
110 return 'invalid'
111
112 @classmethod
113 def require_caches(cls):
114 """Does the CPU model require caches?
115
116 Some CPU models might make assumptions that require them to
117 have caches.
118 """
119 return False
120
121 @classmethod
122 def support_take_over(cls):
123 """Does the CPU model support CPU takeOverFrom?"""
124 return False
125
126 def takeOverFrom(self, old_cpu):
127 self._ccObject.takeOverFrom(old_cpu._ccObject)
128
129
130 system = Param.System(Parent.any, "system object")
131 cpu_id = Param.Int(-1, "CPU identifier")
132 socket_id = Param.Unsigned(0, "Physical Socket identifier")
133 numThreads = Param.Unsigned(1, "number of HW thread contexts")
134
135 function_trace = Param.Bool(False, "Enable function trace")
136 function_trace_start = Param.Tick(0, "Tick to start function trace")
137
138 checker = Param.BaseCPU(NULL, "checker CPU")
139
140 do_checkpoint_insts = Param.Bool(True,
141 "enable checkpoint pseudo instructions")
142 do_statistics_insts = Param.Bool(True,
143 "enable statistics pseudo instructions")
144
145 profile = Param.Latency('0ns', "trace the kernel stack")
146 do_quiesce = Param.Bool(True, "enable quiesce instructions")
147
148 workload = VectorParam.Process([], "processes to run")
149
150 if buildEnv['TARGET_ISA'] == 'sparc':
151 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
152 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
153 interrupts = VectorParam.SparcInterrupts(
154 [], "Interrupt Controller")
155 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
156 elif buildEnv['TARGET_ISA'] == 'alpha':
157 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
158 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
159 interrupts = VectorParam.AlphaInterrupts(
160 [], "Interrupt Controller")
161 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
162 elif buildEnv['TARGET_ISA'] == 'x86':
163 dtb = Param.X86TLB(X86TLB(), "Data TLB")
164 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
165 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
166 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
167 elif buildEnv['TARGET_ISA'] == 'mips':
168 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
169 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
170 interrupts = VectorParam.MipsInterrupts(
171 [], "Interrupt Controller")
172 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
173 elif buildEnv['TARGET_ISA'] == 'arm':
174 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
175 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
176 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
177 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
178 interrupts = VectorParam.ArmInterrupts(
179 [], "Interrupt Controller")
180 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
181 elif buildEnv['TARGET_ISA'] == 'power':
182 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
183 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
184 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
185 interrupts = VectorParam.PowerInterrupts(
186 [], "Interrupt Controller")
187 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
| 93
94class BaseCPU(MemObject):
95 type = 'BaseCPU'
96 abstract = True
97 cxx_header = "cpu/base.hh"
98
99 @classmethod
100 def export_methods(cls, code):
101 code('''
102 void switchOut();
103 void takeOverFrom(BaseCPU *cpu);
104 bool switchedOut();
105 void flushTLBs();
106 Counter totalInsts();
107 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
108 void scheduleLoadStop(ThreadID tid, Counter loads, const char *cause);
109 uint64_t getCurrentInstCount(ThreadID tid);
110''')
111
112 @classmethod
113 def memory_mode(cls):
114 """Which memory mode does this CPU require?"""
115 return 'invalid'
116
117 @classmethod
118 def require_caches(cls):
119 """Does the CPU model require caches?
120
121 Some CPU models might make assumptions that require them to
122 have caches.
123 """
124 return False
125
126 @classmethod
127 def support_take_over(cls):
128 """Does the CPU model support CPU takeOverFrom?"""
129 return False
130
131 def takeOverFrom(self, old_cpu):
132 self._ccObject.takeOverFrom(old_cpu._ccObject)
133
134
135 system = Param.System(Parent.any, "system object")
136 cpu_id = Param.Int(-1, "CPU identifier")
137 socket_id = Param.Unsigned(0, "Physical Socket identifier")
138 numThreads = Param.Unsigned(1, "number of HW thread contexts")
139
140 function_trace = Param.Bool(False, "Enable function trace")
141 function_trace_start = Param.Tick(0, "Tick to start function trace")
142
143 checker = Param.BaseCPU(NULL, "checker CPU")
144
145 do_checkpoint_insts = Param.Bool(True,
146 "enable checkpoint pseudo instructions")
147 do_statistics_insts = Param.Bool(True,
148 "enable statistics pseudo instructions")
149
150 profile = Param.Latency('0ns', "trace the kernel stack")
151 do_quiesce = Param.Bool(True, "enable quiesce instructions")
152
153 workload = VectorParam.Process([], "processes to run")
154
155 if buildEnv['TARGET_ISA'] == 'sparc':
156 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
157 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
158 interrupts = VectorParam.SparcInterrupts(
159 [], "Interrupt Controller")
160 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
161 elif buildEnv['TARGET_ISA'] == 'alpha':
162 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
163 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
164 interrupts = VectorParam.AlphaInterrupts(
165 [], "Interrupt Controller")
166 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
167 elif buildEnv['TARGET_ISA'] == 'x86':
168 dtb = Param.X86TLB(X86TLB(), "Data TLB")
169 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
170 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
171 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
172 elif buildEnv['TARGET_ISA'] == 'mips':
173 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
174 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
175 interrupts = VectorParam.MipsInterrupts(
176 [], "Interrupt Controller")
177 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
178 elif buildEnv['TARGET_ISA'] == 'arm':
179 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
180 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
181 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
182 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
183 interrupts = VectorParam.ArmInterrupts(
184 [], "Interrupt Controller")
185 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
186 elif buildEnv['TARGET_ISA'] == 'power':
187 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
188 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
189 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
190 interrupts = VectorParam.PowerInterrupts(
191 [], "Interrupt Controller")
192 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
|
| 193 elif buildEnv['TARGET_ISA'] == 'riscv':
194 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
195 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
196 interrupts = VectorParam.RiscvInterrupts(
197 [], "Interrupt Controller")
198 isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
|
188 else:
189 print "Don't know what TLB to use for ISA %s" % \
190 buildEnv['TARGET_ISA']
191 sys.exit(1)
192
193 max_insts_all_threads = Param.Counter(0,
194 "terminate when all threads have reached this inst count")
195 max_insts_any_thread = Param.Counter(0,
196 "terminate when any thread reaches this inst count")
197 simpoint_start_insts = VectorParam.Counter([],
198 "starting instruction counts of simpoints")
199 max_loads_all_threads = Param.Counter(0,
200 "terminate when all threads have reached this load count")
201 max_loads_any_thread = Param.Counter(0,
202 "terminate when any thread reaches this load count")
203 progress_interval = Param.Frequency('0Hz',
204 "frequency to print out the progress message")
205
206 switched_out = Param.Bool(False,
207 "Leave the CPU switched out after startup (used when switching " \
208 "between CPU models)")
209
210 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
211
212 icache_port = MasterPort("Instruction Port")
213 dcache_port = MasterPort("Data Port")
214 _cached_ports = ['icache_port', 'dcache_port']
215
216 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
217 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
218
219 _uncached_slave_ports = []
220 _uncached_master_ports = []
221 if buildEnv['TARGET_ISA'] == 'x86':
222 _uncached_slave_ports += ["interrupts[0].pio",
223 "interrupts[0].int_slave"]
224 _uncached_master_ports += ["interrupts[0].int_master"]
225
226 def createInterruptController(self):
227 if buildEnv['TARGET_ISA'] == 'sparc':
228 self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
229 elif buildEnv['TARGET_ISA'] == 'alpha':
230 self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
231 elif buildEnv['TARGET_ISA'] == 'x86':
232 self.apic_clk_domain = DerivedClockDomain(clk_domain =
233 Parent.clk_domain,
234 clk_divider = 16)
235 self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
236 pio_addr=0x2000000000000000)
237 for i in xrange(self.numThreads)]
238 _localApic = self.interrupts
239 elif buildEnv['TARGET_ISA'] == 'mips':
240 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
241 elif buildEnv['TARGET_ISA'] == 'arm':
242 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
243 elif buildEnv['TARGET_ISA'] == 'power':
244 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
| 199 else:
200 print "Don't know what TLB to use for ISA %s" % \
201 buildEnv['TARGET_ISA']
202 sys.exit(1)
203
204 max_insts_all_threads = Param.Counter(0,
205 "terminate when all threads have reached this inst count")
206 max_insts_any_thread = Param.Counter(0,
207 "terminate when any thread reaches this inst count")
208 simpoint_start_insts = VectorParam.Counter([],
209 "starting instruction counts of simpoints")
210 max_loads_all_threads = Param.Counter(0,
211 "terminate when all threads have reached this load count")
212 max_loads_any_thread = Param.Counter(0,
213 "terminate when any thread reaches this load count")
214 progress_interval = Param.Frequency('0Hz',
215 "frequency to print out the progress message")
216
217 switched_out = Param.Bool(False,
218 "Leave the CPU switched out after startup (used when switching " \
219 "between CPU models)")
220
221 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
222
223 icache_port = MasterPort("Instruction Port")
224 dcache_port = MasterPort("Data Port")
225 _cached_ports = ['icache_port', 'dcache_port']
226
227 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
228 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
229
230 _uncached_slave_ports = []
231 _uncached_master_ports = []
232 if buildEnv['TARGET_ISA'] == 'x86':
233 _uncached_slave_ports += ["interrupts[0].pio",
234 "interrupts[0].int_slave"]
235 _uncached_master_ports += ["interrupts[0].int_master"]
236
237 def createInterruptController(self):
238 if buildEnv['TARGET_ISA'] == 'sparc':
239 self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
240 elif buildEnv['TARGET_ISA'] == 'alpha':
241 self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
242 elif buildEnv['TARGET_ISA'] == 'x86':
243 self.apic_clk_domain = DerivedClockDomain(clk_domain =
244 Parent.clk_domain,
245 clk_divider = 16)
246 self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
247 pio_addr=0x2000000000000000)
248 for i in xrange(self.numThreads)]
249 _localApic = self.interrupts
250 elif buildEnv['TARGET_ISA'] == 'mips':
251 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
252 elif buildEnv['TARGET_ISA'] == 'arm':
253 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
254 elif buildEnv['TARGET_ISA'] == 'power':
255 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
|
| 256 elif buildEnv['TARGET_ISA'] == 'riscv':
257 self.interrupts = \
258 [RiscvInterrupts() for i in xrange(self.numThreads)]
|
245 else:
246 print "Don't know what Interrupt Controller to use for ISA %s" % \
247 buildEnv['TARGET_ISA']
248 sys.exit(1)
249
250 def connectCachedPorts(self, bus):
251 for p in self._cached_ports:
252 exec('self.%s = bus.slave' % p)
253
254 def connectUncachedPorts(self, bus):
255 for p in self._uncached_slave_ports:
256 exec('self.%s = bus.master' % p)
257 for p in self._uncached_master_ports:
258 exec('self.%s = bus.slave' % p)
259
260 def connectAllPorts(self, cached_bus, uncached_bus = None):
261 self.connectCachedPorts(cached_bus)
262 if not uncached_bus:
263 uncached_bus = cached_bus
264 self.connectUncachedPorts(uncached_bus)
265
266 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
267 self.icache = ic
268 self.dcache = dc
269 self.icache_port = ic.cpu_side
270 self.dcache_port = dc.cpu_side
271 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
272 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
273 if iwc and dwc:
274 self.itb_walker_cache = iwc
275 self.dtb_walker_cache = dwc
276 self.itb.walker.port = iwc.cpu_side
277 self.dtb.walker.port = dwc.cpu_side
278 self._cached_ports += ["itb_walker_cache.mem_side", \
279 "dtb_walker_cache.mem_side"]
280 else:
281 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
282
283 # Checker doesn't need its own tlb caches because it does
284 # functional accesses only
285 if self.checker != NULL:
286 self._cached_ports += ["checker.itb.walker.port", \
287 "checker.dtb.walker.port"]
288
289 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
290 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
291 self.toL2Bus = L2XBar()
292 self.connectCachedPorts(self.toL2Bus)
293 self.l2cache = l2c
294 self.toL2Bus.master = self.l2cache.cpu_side
295 self._cached_ports = ['l2cache.mem_side']
296
297 def createThreads(self):
298 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
299 if self.checker != NULL:
300 self.checker.createThreads()
301
302 def addCheckerCpu(self):
303 pass
| 259 else:
260 print "Don't know what Interrupt Controller to use for ISA %s" % \
261 buildEnv['TARGET_ISA']
262 sys.exit(1)
263
264 def connectCachedPorts(self, bus):
265 for p in self._cached_ports:
266 exec('self.%s = bus.slave' % p)
267
268 def connectUncachedPorts(self, bus):
269 for p in self._uncached_slave_ports:
270 exec('self.%s = bus.master' % p)
271 for p in self._uncached_master_ports:
272 exec('self.%s = bus.slave' % p)
273
274 def connectAllPorts(self, cached_bus, uncached_bus = None):
275 self.connectCachedPorts(cached_bus)
276 if not uncached_bus:
277 uncached_bus = cached_bus
278 self.connectUncachedPorts(uncached_bus)
279
280 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
281 self.icache = ic
282 self.dcache = dc
283 self.icache_port = ic.cpu_side
284 self.dcache_port = dc.cpu_side
285 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
286 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
287 if iwc and dwc:
288 self.itb_walker_cache = iwc
289 self.dtb_walker_cache = dwc
290 self.itb.walker.port = iwc.cpu_side
291 self.dtb.walker.port = dwc.cpu_side
292 self._cached_ports += ["itb_walker_cache.mem_side", \
293 "dtb_walker_cache.mem_side"]
294 else:
295 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
296
297 # Checker doesn't need its own tlb caches because it does
298 # functional accesses only
299 if self.checker != NULL:
300 self._cached_ports += ["checker.itb.walker.port", \
301 "checker.dtb.walker.port"]
302
303 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
304 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
305 self.toL2Bus = L2XBar()
306 self.connectCachedPorts(self.toL2Bus)
307 self.l2cache = l2c
308 self.toL2Bus.master = self.l2cache.cpu_side
309 self._cached_ports = ['l2cache.mem_side']
310
311 def createThreads(self):
312 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
313 if self.checker != NULL:
314 self.checker.createThreads()
315
316 def addCheckerCpu(self):
317 pass
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