BaseCPU.py (8745:575cab0db076) | BaseCPU.py (8752:28e899b7dee3) |
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1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 126 unchanged lines hidden (view full) --- 135 "defer registration with system (for sampling)") 136 137 clock = Param.Clock('1t', "clock speed") 138 phase = Param.Latency('0ns', "clock phase") 139 140 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 141 142 _cached_ports = [] | 1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# Copyright (c) 2011 Regents of the University of California 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; --- 126 unchanged lines hidden (view full) --- 135 "defer registration with system (for sampling)") 136 137 clock = Param.Clock('1t', "clock speed") 138 phase = Param.Latency('0ns', "clock phase") 139 140 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 141 142 _cached_ports = [] |
143 if buildEnv['TARGET_ISA'] in ['x86', 'arm'] and buildEnv['FULL_SYSTEM']: | 143 if buildEnv['TARGET_ISA'] == 'x86' or \ 144 (buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']): |
144 _cached_ports = ["itb.walker.port", "dtb.walker.port"] 145 146 _uncached_ports = [] 147 if buildEnv['TARGET_ISA'] == 'x86': 148 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 149 150 def connectCachedPorts(self, bus): 151 for p in self._cached_ports: --- 37 unchanged lines hidden --- | 145 _cached_ports = ["itb.walker.port", "dtb.walker.port"] 146 147 _uncached_ports = [] 148 if buildEnv['TARGET_ISA'] == 'x86': 149 _uncached_ports = ["interrupts.pio", "interrupts.int_port"] 150 151 def connectCachedPorts(self, bus): 152 for p in self._cached_ports: --- 37 unchanged lines hidden --- |