BaseCPU.py (6116:a5a97b04d796) | BaseCPU.py (6654:4c84e771cca7) |
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1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 12 unchanged lines hidden (view full) --- 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 | 1# Copyright (c) 2005-2008 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 12 unchanged lines hidden (view full) --- 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Nathan Binkert 28 |
29from MemObject import MemObject | 29import sys 30 31from m5.defines import buildEnv |
30from m5.params import * 31from m5.proxy import * | 32from m5.params import * 33from m5.proxy import * |
32from m5 import build_env | 34 |
33from Bus import Bus 34from InstTracer import InstTracer 35from ExeTracer import ExeTracer | 35from Bus import Bus 36from InstTracer import InstTracer 37from ExeTracer import ExeTracer |
36import sys | 38from MemObject import MemObject |
37 38default_tracer = ExeTracer() 39 | 39 40default_tracer = ExeTracer() 41 |
40if build_env['TARGET_ISA'] == 'alpha': | 42if buildEnv['TARGET_ISA'] == 'alpha': |
41 from AlphaTLB import AlphaDTB, AlphaITB | 43 from AlphaTLB import AlphaDTB, AlphaITB |
42 if build_env['FULL_SYSTEM']: | 44 if buildEnv['FULL_SYSTEM']: |
43 from AlphaInterrupts import AlphaInterrupts | 45 from AlphaInterrupts import AlphaInterrupts |
44elif build_env['TARGET_ISA'] == 'sparc': | 46elif buildEnv['TARGET_ISA'] == 'sparc': |
45 from SparcTLB import SparcTLB | 47 from SparcTLB import SparcTLB |
46 if build_env['FULL_SYSTEM']: | 48 if buildEnv['FULL_SYSTEM']: |
47 from SparcInterrupts import SparcInterrupts | 49 from SparcInterrupts import SparcInterrupts |
48elif build_env['TARGET_ISA'] == 'x86': | 50elif buildEnv['TARGET_ISA'] == 'x86': |
49 from X86TLB import X86TLB | 51 from X86TLB import X86TLB |
50 if build_env['FULL_SYSTEM']: | 52 if buildEnv['FULL_SYSTEM']: |
51 from X86LocalApic import X86LocalApic | 53 from X86LocalApic import X86LocalApic |
52elif build_env['TARGET_ISA'] == 'mips': | 54elif buildEnv['TARGET_ISA'] == 'mips': |
53 from MipsTLB import MipsTLB | 55 from MipsTLB import MipsTLB |
54 if build_env['FULL_SYSTEM']: | 56 if buildEnv['FULL_SYSTEM']: |
55 from MipsInterrupts import MipsInterrupts | 57 from MipsInterrupts import MipsInterrupts |
56elif build_env['TARGET_ISA'] == 'arm': | 58elif buildEnv['TARGET_ISA'] == 'arm': |
57 from ArmTLB import ArmTLB | 59 from ArmTLB import ArmTLB |
58 if build_env['FULL_SYSTEM']: | 60 if buildEnv['FULL_SYSTEM']: |
59 from ArmInterrupts import ArmInterrupts 60 61class BaseCPU(MemObject): 62 type = 'BaseCPU' 63 abstract = True 64 65 system = Param.System(Parent.any, "system object") 66 cpu_id = Param.Int(-1, "CPU identifier") --- 4 unchanged lines hidden (view full) --- 71 72 checker = Param.BaseCPU(NULL, "checker CPU") 73 74 do_checkpoint_insts = Param.Bool(True, 75 "enable checkpoint pseudo instructions") 76 do_statistics_insts = Param.Bool(True, 77 "enable statistics pseudo instructions") 78 | 61 from ArmInterrupts import ArmInterrupts 62 63class BaseCPU(MemObject): 64 type = 'BaseCPU' 65 abstract = True 66 67 system = Param.System(Parent.any, "system object") 68 cpu_id = Param.Int(-1, "CPU identifier") --- 4 unchanged lines hidden (view full) --- 73 74 checker = Param.BaseCPU(NULL, "checker CPU") 75 76 do_checkpoint_insts = Param.Bool(True, 77 "enable checkpoint pseudo instructions") 78 do_statistics_insts = Param.Bool(True, 79 "enable statistics pseudo instructions") 80 |
79 if build_env['FULL_SYSTEM']: | 81 if buildEnv['FULL_SYSTEM']: |
80 profile = Param.Latency('0ns', "trace the kernel stack") 81 do_quiesce = Param.Bool(True, "enable quiesce instructions") 82 else: 83 workload = VectorParam.Process("processes to run") 84 | 82 profile = Param.Latency('0ns', "trace the kernel stack") 83 do_quiesce = Param.Bool(True, "enable quiesce instructions") 84 else: 85 workload = VectorParam.Process("processes to run") 86 |
85 if build_env['TARGET_ISA'] == 'sparc': | 87 if buildEnv['TARGET_ISA'] == 'sparc': |
86 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 87 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") | 88 dtb = Param.SparcTLB(SparcTLB(), "Data TLB") 89 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB") |
88 if build_env['FULL_SYSTEM']: | 90 if buildEnv['FULL_SYSTEM']: |
89 interrupts = Param.SparcInterrupts( 90 SparcInterrupts(), "Interrupt Controller") | 91 interrupts = Param.SparcInterrupts( 92 SparcInterrupts(), "Interrupt Controller") |
91 elif build_env['TARGET_ISA'] == 'alpha': | 93 elif buildEnv['TARGET_ISA'] == 'alpha': |
92 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 93 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") | 94 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB") 95 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB") |
94 if build_env['FULL_SYSTEM']: | 96 if buildEnv['FULL_SYSTEM']: |
95 interrupts = Param.AlphaInterrupts( 96 AlphaInterrupts(), "Interrupt Controller") | 97 interrupts = Param.AlphaInterrupts( 98 AlphaInterrupts(), "Interrupt Controller") |
97 elif build_env['TARGET_ISA'] == 'x86': | 99 elif buildEnv['TARGET_ISA'] == 'x86': |
98 dtb = Param.X86TLB(X86TLB(), "Data TLB") 99 itb = Param.X86TLB(X86TLB(), "Instruction TLB") | 100 dtb = Param.X86TLB(X86TLB(), "Data TLB") 101 itb = Param.X86TLB(X86TLB(), "Instruction TLB") |
100 if build_env['FULL_SYSTEM']: | 102 if buildEnv['FULL_SYSTEM']: |
101 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 102 interrupts = \ 103 Param.X86LocalApic(_localApic, "Interrupt Controller") | 103 _localApic = X86LocalApic(pio_addr=0x2000000000000000) 104 interrupts = \ 105 Param.X86LocalApic(_localApic, "Interrupt Controller") |
104 elif build_env['TARGET_ISA'] == 'mips': | 106 elif buildEnv['TARGET_ISA'] == 'mips': |
105 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 106 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") | 107 dtb = Param.MipsTLB(MipsTLB(), "Data TLB") 108 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB") |
107 if build_env['FULL_SYSTEM']: | 109 if buildEnv['FULL_SYSTEM']: |
108 interrupts = Param.MipsInterrupts( 109 MipsInterrupts(), "Interrupt Controller") | 110 interrupts = Param.MipsInterrupts( 111 MipsInterrupts(), "Interrupt Controller") |
110 elif build_env['TARGET_ISA'] == 'arm': | 112 elif buildEnv['TARGET_ISA'] == 'arm': |
111 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 112 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 113 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") | 113 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?") 114 dtb = Param.ArmTLB(ArmTLB(), "Data TLB") 115 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB") |
114 if build_env['FULL_SYSTEM']: | 116 if buildEnv['FULL_SYSTEM']: |
115 interrupts = Param.ArmInterrupts( 116 ArmInterrupts(), "Interrupt Controller") 117 else: 118 print "Don't know what TLB to use for ISA %s" % \ | 117 interrupts = Param.ArmInterrupts( 118 ArmInterrupts(), "Interrupt Controller") 119 else: 120 print "Don't know what TLB to use for ISA %s" % \ |
119 build_env['TARGET_ISA'] | 121 buildEnv['TARGET_ISA'] |
120 sys.exit(1) 121 122 max_insts_all_threads = Param.Counter(0, 123 "terminate when all threads have reached this inst count") 124 max_insts_any_thread = Param.Counter(0, 125 "terminate when any thread reaches this inst count") 126 max_loads_all_threads = Param.Counter(0, 127 "terminate when all threads have reached this load count") --- 6 unchanged lines hidden (view full) --- 134 "defer registration with system (for sampling)") 135 136 clock = Param.Clock('1t', "clock speed") 137 phase = Param.Latency('0ns', "clock phase") 138 139 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 140 141 _mem_ports = [] | 122 sys.exit(1) 123 124 max_insts_all_threads = Param.Counter(0, 125 "terminate when all threads have reached this inst count") 126 max_insts_any_thread = Param.Counter(0, 127 "terminate when any thread reaches this inst count") 128 max_loads_all_threads = Param.Counter(0, 129 "terminate when all threads have reached this load count") --- 6 unchanged lines hidden (view full) --- 136 "defer registration with system (for sampling)") 137 138 clock = Param.Clock('1t', "clock speed") 139 phase = Param.Latency('0ns', "clock phase") 140 141 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 142 143 _mem_ports = [] |
142 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: | 144 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: |
143 _mem_ports = ["itb.walker.port", 144 "dtb.walker.port", 145 "interrupts.pio", 146 "interrupts.int_port"] 147 148 def connectMemPorts(self, bus): 149 for p in self._mem_ports: 150 if p != 'physmem_port': 151 exec('self.%s = bus.port' % p) 152 153 def addPrivateSplitL1Caches(self, ic, dc): 154 assert(len(self._mem_ports) < 6) 155 self.icache = ic 156 self.dcache = dc 157 self.icache_port = ic.cpu_side 158 self.dcache_port = dc.cpu_side 159 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] | 145 _mem_ports = ["itb.walker.port", 146 "dtb.walker.port", 147 "interrupts.pio", 148 "interrupts.int_port"] 149 150 def connectMemPorts(self, bus): 151 for p in self._mem_ports: 152 if p != 'physmem_port': 153 exec('self.%s = bus.port' % p) 154 155 def addPrivateSplitL1Caches(self, ic, dc): 156 assert(len(self._mem_ports) < 6) 157 self.icache = ic 158 self.dcache = dc 159 self.icache_port = ic.cpu_side 160 self.dcache_port = dc.cpu_side 161 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] |
160 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: | 162 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']: |
161 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 162 163 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 164 self.addPrivateSplitL1Caches(ic, dc) 165 self.toL2Bus = Bus() 166 self.connectMemPorts(self.toL2Bus) 167 self.l2cache = l2c 168 self.l2cache.cpu_side = self.toL2Bus.port 169 self._mem_ports = ['l2cache.mem_side'] 170 | 163 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 164 165 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 166 self.addPrivateSplitL1Caches(ic, dc) 167 self.toL2Bus = Bus() 168 self.connectMemPorts(self.toL2Bus) 169 self.l2cache = l2c 170 self.l2cache.cpu_side = self.toL2Bus.port 171 self._mem_ports = ['l2cache.mem_side'] 172 |
171 if build_env['TARGET_ISA'] == 'mips': | 173 if buildEnv['TARGET_ISA'] == 'mips': |
172 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 173 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 174 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 175 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 176 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 177 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 178 CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 179 CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") --- 46 unchanged lines hidden --- | 174 CP0_IntCtl_IPTI = Param.Unsigned(0,"No Description") 175 CP0_IntCtl_IPPCI = Param.Unsigned(0,"No Description") 176 CP0_SrsCtl_HSS = Param.Unsigned(0,"No Description") 177 CP0_EBase_CPUNum = Param.Unsigned(0,"No Description") 178 CP0_PRId_CompanyOptions = Param.Unsigned(0,"Company Options in Processor ID Register") 179 CP0_PRId_CompanyID = Param.Unsigned(0,"Company Identifier in Processor ID Register") 180 CP0_PRId_ProcessorID = Param.Unsigned(1,"Processor ID (0=>Not MIPS32/64 Processor, 1=>MIPS, 2-255 => Other Company") 181 CP0_PRId_Revision = Param.Unsigned(0,"Processor Revision Number in Processor ID Register") --- 46 unchanged lines hidden --- |