BaseCPU.py (5236:0050ad4fb3ef) | BaseCPU.py (5237:6c819dbe8045) |
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1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 86 unchanged lines hidden (view full) --- 95 96 clock = Param.Clock('1t', "clock speed") 97 phase = Param.Latency('0ns', "clock phase") 98 99 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 100 101 _mem_ports = [] 102 | 1# Copyright (c) 2005-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 86 unchanged lines hidden (view full) --- 95 96 clock = Param.Clock('1t', "clock speed") 97 phase = Param.Latency('0ns', "clock phase") 98 99 tracer = Param.InstTracer(default_tracer, "Instruction tracer") 100 101 _mem_ports = [] 102 |
103 if build_env['TARGET_ISA'] == 'x86': | 103 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: |
104 itb.walker_port = Port("ITB page table walker port") 105 dtb.walker_port = Port("ITB page table walker port") 106 _mem_ports = ["itb.walker_port", "dtb.walker_port"] 107 108 def connectMemPorts(self, bus): 109 for p in self._mem_ports: 110 if p != 'physmem_port': 111 exec('self.%s = bus.port' % p) 112 113 def addPrivateSplitL1Caches(self, ic, dc): 114 assert(len(self._mem_ports) < 6) 115 self.icache = ic 116 self.dcache = dc 117 self.icache_port = ic.cpu_side 118 self.dcache_port = dc.cpu_side 119 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] | 104 itb.walker_port = Port("ITB page table walker port") 105 dtb.walker_port = Port("ITB page table walker port") 106 _mem_ports = ["itb.walker_port", "dtb.walker_port"] 107 108 def connectMemPorts(self, bus): 109 for p in self._mem_ports: 110 if p != 'physmem_port': 111 exec('self.%s = bus.port' % p) 112 113 def addPrivateSplitL1Caches(self, ic, dc): 114 assert(len(self._mem_ports) < 6) 115 self.icache = ic 116 self.dcache = dc 117 self.icache_port = ic.cpu_side 118 self.dcache_port = dc.cpu_side 119 self._mem_ports = ['icache.mem_side', 'dcache.mem_side'] |
120 if build_env['TARGET_ISA'] == 'x86': | 120 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']: |
121 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 122 123 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 124 self.addPrivateSplitL1Caches(ic, dc) 125 self.toL2Bus = Bus() 126 self.connectMemPorts(self.toL2Bus) 127 self.l2cache = l2c 128 self.l2cache.cpu_side = self.toL2Bus.port 129 self._mem_ports = ['l2cache.mem_side'] | 121 self._mem_ports += ["itb.walker_port", "dtb.walker_port"] 122 123 def addTwoLevelCacheHierarchy(self, ic, dc, l2c): 124 self.addPrivateSplitL1Caches(ic, dc) 125 self.toL2Bus = Bus() 126 self.connectMemPorts(self.toL2Bus) 127 self.l2cache = l2c 128 self.l2cache.cpu_side = self.toL2Bus.port 129 self._mem_ports = ['l2cache.mem_side'] |