1# Copyright (c) 2012-2013, 2015-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2008 The Regents of The University of Michigan
14# Copyright (c) 2011 Regents of the University of California
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
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26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Nathan Binkert
41# Rick Strong
42# Andreas Hansson
43
44import sys
45
46from m5.SimObject import *
47from m5.defines import buildEnv
48from m5.params import *
49from m5.proxy import *
50
51from XBar import L2XBar
52from InstTracer import InstTracer
53from CPUTracers import ExeTracer
54from MemObject import MemObject
55from ClockDomain import *
56
57default_tracer = ExeTracer()
58
59if buildEnv['TARGET_ISA'] == 'alpha':
60 from AlphaTLB import AlphaDTB, AlphaITB
61 from AlphaInterrupts import AlphaInterrupts
62 from AlphaISA import AlphaISA
63 isa_class = AlphaISA
64elif buildEnv['TARGET_ISA'] == 'sparc':
65 from SparcTLB import SparcTLB
66 from SparcInterrupts import SparcInterrupts
67 from SparcISA import SparcISA
68 isa_class = SparcISA
69elif buildEnv['TARGET_ISA'] == 'x86':
70 from X86TLB import X86TLB
71 from X86LocalApic import X86LocalApic
72 from X86ISA import X86ISA
73 isa_class = X86ISA
74elif buildEnv['TARGET_ISA'] == 'mips':
75 from MipsTLB import MipsTLB
76 from MipsInterrupts import MipsInterrupts
77 from MipsISA import MipsISA
78 isa_class = MipsISA
79elif buildEnv['TARGET_ISA'] == 'arm':
80 from ArmTLB import ArmTLB, ArmStage2IMMU, ArmStage2DMMU
81 from ArmInterrupts import ArmInterrupts
82 from ArmISA import ArmISA
83 isa_class = ArmISA
84elif buildEnv['TARGET_ISA'] == 'power':
85 from PowerTLB import PowerTLB
86 from PowerInterrupts import PowerInterrupts
87 from PowerISA import PowerISA
88 isa_class = PowerISA
89elif buildEnv['TARGET_ISA'] == 'riscv':
90 from RiscvTLB import RiscvTLB
91 from RiscvInterrupts import RiscvInterrupts
92 from RiscvISA import RiscvISA
93 isa_class = RiscvISA
94
95class BaseCPU(MemObject):
96 type = 'BaseCPU'
97 abstract = True
98 cxx_header = "cpu/base.hh"
99
100 cxx_exports = [
101 PyBindMethod("switchOut"),
102 PyBindMethod("takeOverFrom"),
103 PyBindMethod("switchedOut"),
104 PyBindMethod("flushTLBs"),
105 PyBindMethod("totalInsts"),
106 PyBindMethod("scheduleInstStop"),
107 PyBindMethod("scheduleLoadStop"),
108 PyBindMethod("getCurrentInstCount"),
109 ]
110
111 @classmethod
112 def memory_mode(cls):
113 """Which memory mode does this CPU require?"""
114 return 'invalid'
115
116 @classmethod
117 def require_caches(cls):
118 """Does the CPU model require caches?
119
120 Some CPU models might make assumptions that require them to
121 have caches.
122 """
123 return False
124
125 @classmethod
126 def support_take_over(cls):
127 """Does the CPU model support CPU takeOverFrom?"""
128 return False
129
130 def takeOverFrom(self, old_cpu):
131 self._ccObject.takeOverFrom(old_cpu._ccObject)
132
133
134 system = Param.System(Parent.any, "system object")
135 cpu_id = Param.Int(-1, "CPU identifier")
136 socket_id = Param.Unsigned(0, "Physical Socket identifier")
137 numThreads = Param.Unsigned(1, "number of HW thread contexts")
138 pwr_gating_latency = Param.Cycles(300,
139 "Latency to enter power gating state when all contexts are suspended")
140
141 function_trace = Param.Bool(False, "Enable function trace")
142 function_trace_start = Param.Tick(0, "Tick to start function trace")
143
144 checker = Param.BaseCPU(NULL, "checker CPU")
145
146 syscallRetryLatency = Param.Cycles(10000, "Cycles to wait until retry")
147
148 do_checkpoint_insts = Param.Bool(True,
149 "enable checkpoint pseudo instructions")
150 do_statistics_insts = Param.Bool(True,
151 "enable statistics pseudo instructions")
152
153 profile = Param.Latency('0ns', "trace the kernel stack")
154 do_quiesce = Param.Bool(True, "enable quiesce instructions")
155
156 wait_for_remote_gdb = Param.Bool(False,
157 "Wait for a remote GDB connection");
158
159 workload = VectorParam.Process([], "processes to run")
160
161 if buildEnv['TARGET_ISA'] == 'sparc':
162 dtb = Param.SparcTLB(SparcTLB(), "Data TLB")
163 itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
164 interrupts = VectorParam.SparcInterrupts(
165 [], "Interrupt Controller")
166 isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
167 elif buildEnv['TARGET_ISA'] == 'alpha':
168 dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
169 itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
170 interrupts = VectorParam.AlphaInterrupts(
171 [], "Interrupt Controller")
172 isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
173 elif buildEnv['TARGET_ISA'] == 'x86':
174 dtb = Param.X86TLB(X86TLB(), "Data TLB")
175 itb = Param.X86TLB(X86TLB(), "Instruction TLB")
176 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
177 isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
178 elif buildEnv['TARGET_ISA'] == 'mips':
179 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
180 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
181 interrupts = VectorParam.MipsInterrupts(
182 [], "Interrupt Controller")
183 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
184 elif buildEnv['TARGET_ISA'] == 'arm':
185 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
186 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
187 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
188 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
189 interrupts = VectorParam.ArmInterrupts(
190 [], "Interrupt Controller")
191 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
192 elif buildEnv['TARGET_ISA'] == 'power':
193 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
194 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
195 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
196 interrupts = VectorParam.PowerInterrupts(
197 [], "Interrupt Controller")
198 isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
199 elif buildEnv['TARGET_ISA'] == 'riscv':
200 dtb = Param.RiscvTLB(RiscvTLB(), "Data TLB")
201 itb = Param.RiscvTLB(RiscvTLB(), "Instruction TLB")
202 interrupts = VectorParam.RiscvInterrupts(
203 [], "Interrupt Controller")
204 isa = VectorParam.RiscvISA([ isa_class() ], "ISA instance")
205 else:
206 print "Don't know what TLB to use for ISA %s" % \
207 buildEnv['TARGET_ISA']
208 sys.exit(1)
209
210 max_insts_all_threads = Param.Counter(0,
211 "terminate when all threads have reached this inst count")
212 max_insts_any_thread = Param.Counter(0,
213 "terminate when any thread reaches this inst count")
214 simpoint_start_insts = VectorParam.Counter([],
215 "starting instruction counts of simpoints")
216 max_loads_all_threads = Param.Counter(0,
217 "terminate when all threads have reached this load count")
218 max_loads_any_thread = Param.Counter(0,
219 "terminate when any thread reaches this load count")
220 progress_interval = Param.Frequency('0Hz',
221 "frequency to print out the progress message")
222
223 switched_out = Param.Bool(False,
224 "Leave the CPU switched out after startup (used when switching " \
225 "between CPU models)")
226
227 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
228
229 icache_port = MasterPort("Instruction Port")
230 dcache_port = MasterPort("Data Port")
231 _cached_ports = ['icache_port', 'dcache_port']
232
233 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
234 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
235
236 _uncached_slave_ports = []
237 _uncached_master_ports = []
238 if buildEnv['TARGET_ISA'] == 'x86':
239 _uncached_slave_ports += ["interrupts[0].pio",
240 "interrupts[0].int_slave"]
241 _uncached_master_ports += ["interrupts[0].int_master"]
242
243 def createInterruptController(self):
244 if buildEnv['TARGET_ISA'] == 'sparc':
245 self.interrupts = [SparcInterrupts() for i in xrange(self.numThreads)]
246 elif buildEnv['TARGET_ISA'] == 'alpha':
247 self.interrupts = [AlphaInterrupts() for i in xrange(self.numThreads)]
248 elif buildEnv['TARGET_ISA'] == 'x86':
249 self.apic_clk_domain = DerivedClockDomain(clk_domain =
250 Parent.clk_domain,
251 clk_divider = 16)
252 self.interrupts = [X86LocalApic(clk_domain = self.apic_clk_domain,
253 pio_addr=0x2000000000000000)
254 for i in xrange(self.numThreads)]
255 _localApic = self.interrupts
256 elif buildEnv['TARGET_ISA'] == 'mips':
257 self.interrupts = [MipsInterrupts() for i in xrange(self.numThreads)]
258 elif buildEnv['TARGET_ISA'] == 'arm':
259 self.interrupts = [ArmInterrupts() for i in xrange(self.numThreads)]
260 elif buildEnv['TARGET_ISA'] == 'power':
261 self.interrupts = [PowerInterrupts() for i in xrange(self.numThreads)]
262 elif buildEnv['TARGET_ISA'] == 'riscv':
263 self.interrupts = \
264 [RiscvInterrupts() for i in xrange(self.numThreads)]
265 else:
266 print "Don't know what Interrupt Controller to use for ISA %s" % \
267 buildEnv['TARGET_ISA']
268 sys.exit(1)
269
270 def connectCachedPorts(self, bus):
271 for p in self._cached_ports:
272 exec('self.%s = bus.slave' % p)
273
274 def connectUncachedPorts(self, bus):
275 for p in self._uncached_slave_ports:
276 exec('self.%s = bus.master' % p)
277 for p in self._uncached_master_ports:
278 exec('self.%s = bus.slave' % p)
279
280 def connectAllPorts(self, cached_bus, uncached_bus = None):
281 self.connectCachedPorts(cached_bus)
282 if not uncached_bus:
283 uncached_bus = cached_bus
284 self.connectUncachedPorts(uncached_bus)
285
286 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
287 self.icache = ic
288 self.dcache = dc
289 self.icache_port = ic.cpu_side
290 self.dcache_port = dc.cpu_side
291 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
292 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
293 if iwc and dwc:
294 self.itb_walker_cache = iwc
295 self.dtb_walker_cache = dwc
296 self.itb.walker.port = iwc.cpu_side
297 self.dtb.walker.port = dwc.cpu_side
298 self._cached_ports += ["itb_walker_cache.mem_side", \
299 "dtb_walker_cache.mem_side"]
300 else:
301 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
302
303 # Checker doesn't need its own tlb caches because it does
304 # functional accesses only
305 if self.checker != NULL:
306 self._cached_ports += ["checker.itb.walker.port", \
307 "checker.dtb.walker.port"]
308
309 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
310 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
311 self.toL2Bus = L2XBar()
312 self.connectCachedPorts(self.toL2Bus)
313 self.l2cache = l2c
314 self.toL2Bus.master = self.l2cache.cpu_side
315 self._cached_ports = ['l2cache.mem_side']
316
317 def createThreads(self):
318 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
319 if self.checker != NULL:
320 self.checker.createThreads()
321
322 def addCheckerCpu(self):
323 pass