1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

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71 from X86ISA import X86ISA
72 isa_class = X86ISA
73elif buildEnv['TARGET_ISA'] == 'mips':
74 from MipsTLB import MipsTLB
75 from MipsInterrupts import MipsInterrupts
76 from MipsISA import MipsISA
77 isa_class = MipsISA
78elif buildEnv['TARGET_ISA'] == 'arm':
79 from ArmTLB import ArmTLB
80 from ArmInterrupts import ArmInterrupts
81 from ArmISA import ArmISA
82 isa_class = ArmISA
83elif buildEnv['TARGET_ISA'] == 'power':
84 from PowerTLB import PowerTLB
85 from PowerInterrupts import PowerInterrupts
86 from PowerISA import PowerISA
87 isa_class = PowerISA

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166 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
167 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
168 interrupts = Param.MipsInterrupts(
169 NULL, "Interrupt Controller")
170 isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
171 elif buildEnv['TARGET_ISA'] == 'arm':
172 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
173 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
174 interrupts = Param.ArmInterrupts(
175 NULL, "Interrupt Controller")
176 isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
177 elif buildEnv['TARGET_ISA'] == 'power':
178 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
179 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
180 itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
181 interrupts = Param.PowerInterrupts(

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206 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
207
208 icache_port = MasterPort("Instruction Port")
209 dcache_port = MasterPort("Data Port")
210 _cached_ports = ['icache_port', 'dcache_port']
211
212 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
213 _cached_ports += ["itb.walker.port", "dtb.walker.port"]
214
215 _uncached_slave_ports = []
216 _uncached_master_ports = []
217 if buildEnv['TARGET_ISA'] == 'x86':
218 _uncached_slave_ports += ["interrupts.pio", "interrupts.int_slave"]
219 _uncached_master_ports += ["interrupts.int_master"]
220
221 def createInterruptController(self):

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262 self.dcache = dc
263 self.icache_port = ic.cpu_side
264 self.dcache_port = dc.cpu_side
265 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
266 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
267 if iwc and dwc:
268 self.itb_walker_cache = iwc
269 self.dtb_walker_cache = dwc
270 self.itb.walker.port = iwc.cpu_side
271 self.dtb.walker.port = dwc.cpu_side
272 self._cached_ports += ["itb_walker_cache.mem_side", \
273 "dtb_walker_cache.mem_side"]
274 else:
275 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
276
277 # Checker doesn't need its own tlb caches because it does
278 # functional accesses only
279 if self.checker != NULL:
280 self._cached_ports += ["checker.itb.walker.port", \
281 "checker.dtb.walker.port"]
282
283 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
284 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
285 # Set a width of 32 bytes (256-bits), which is four times that
286 # of the default bus. The clock of the CPU is inherited by
287 # default.
288 self.toL2Bus = CoherentBus(width = 32)
289 self.connectCachedPorts(self.toL2Bus)
290 self.l2cache = l2c
291 self.toL2Bus.master = self.l2cache.cpu_side
292 self._cached_ports = ['l2cache.mem_side']
293
294 def createThreads(self):
295 self.isa = [ isa_class() for i in xrange(self.numThreads) ]
296 if self.checker != NULL:
297 self.checker.createThreads()
298
299 def addCheckerCpu(self):
300 pass