1# Copyright (c) 2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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231 # Checker doesn't need its own tlb caches because it does
232 # functional accesses only
233 if self.checker != NULL:
234 self._cached_ports += ["checker.itb.walker.port", \
235 "checker.dtb.walker.port"]
236
237 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
238 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
239 self.toL2Bus = CoherentBus()
240 self.connectCachedPorts(self.toL2Bus)
241 self.l2cache = l2c
242 self.toL2Bus.master = self.l2cache.cpu_side
243 self._cached_ports = ['l2cache.mem_side']
244
245 def addCheckerCpu(self):
246 pass