1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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92 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
93 if build_env['FULL_SYSTEM']:
94 interrupts = Param.AlphaInterrupts(
95 AlphaInterrupts(), "Interrupt Controller")
96 elif build_env['TARGET_ISA'] == 'x86':
97 dtb = Param.X86DTB(X86DTB(), "Data TLB")
98 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
99 if build_env['FULL_SYSTEM']:
100 interrupts = Param.X86LocalApic(
101 X86LocalApic(), "Interrupt Controller")
102 elif build_env['TARGET_ISA'] == 'mips':
103 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
104 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
105 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
106 tlb = Param.MipsUTB(MipsUTB(), "Unified TLB")
107 if build_env['FULL_SYSTEM']:
108 interrupts = Param.MipsInterrupts(
109 MipsInterrupts(), "Interrupt Controller")

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136
137 clock = Param.Clock('1t', "clock speed")
138 phase = Param.Latency('0ns', "clock phase")
139
140 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
141
142 _mem_ports = []
143 if build_env['TARGET_ISA'] == 'x86' and build_env['FULL_SYSTEM']:
144 _mem_ports = ["itb.walker.port", "dtb.walker.port"]
145
146 def connectMemPorts(self, bus):
147 for p in self._mem_ports:
148 if p != 'physmem_port':
149 exec('self.%s = bus.port' % p)
150
151 def addPrivateSplitL1Caches(self, ic, dc):
152 assert(len(self._mem_ports) < 6)

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