1# Copyright (c) 2012-2013, 2015-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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59from m5.objects.SubSystem import SubSystem
60from m5.objects.ClockDomain import *
61from m5.objects.Platform import Platform
62
63default_tracer = ExeTracer()
64
65if buildEnv['TARGET_ISA'] == 'alpha':
66 from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
67 from m5.objects.AlphaInterrupts import AlphaInterrupts
68 from m5.objects.AlphaISA import AlphaISA
69 default_isa_class = AlphaISA
70elif buildEnv['TARGET_ISA'] == 'sparc':
71 from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
72 from m5.objects.SparcInterrupts import SparcInterrupts
73 from m5.objects.SparcISA import SparcISA
74 default_isa_class = SparcISA
75elif buildEnv['TARGET_ISA'] == 'x86':
76 from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
77 from m5.objects.X86LocalApic import X86LocalApic
78 from m5.objects.X86ISA import X86ISA
79 default_isa_class = X86ISA
80elif buildEnv['TARGET_ISA'] == 'mips':
81 from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
82 from m5.objects.MipsInterrupts import MipsInterrupts
83 from m5.objects.MipsISA import MipsISA
84 default_isa_class = MipsISA
85elif buildEnv['TARGET_ISA'] == 'arm':
86 from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
87 from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
88 from m5.objects.ArmInterrupts import ArmInterrupts
89 from m5.objects.ArmISA import ArmISA
90 default_isa_class = ArmISA
91elif buildEnv['TARGET_ISA'] == 'power':
92 from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
93 from m5.objects.PowerInterrupts import PowerInterrupts
94 from m5.objects.PowerISA import PowerISA
95 default_isa_class = PowerISA
96elif buildEnv['TARGET_ISA'] == 'riscv':
97 from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
98 from m5.objects.RiscvInterrupts import RiscvInterrupts
99 from m5.objects.RiscvISA import RiscvISA
100 default_isa_class = RiscvISA
101
102class BaseCPU(ClockedObject):
103 type = 'BaseCPU'
104 abstract = True
105 cxx_header = "cpu/base.hh"
106
107 cxx_exports = [
108 PyBindMethod("switchOut"),

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166
167 wait_for_remote_gdb = Param.Bool(False,
168 "Wait for a remote GDB connection");
169
170 workload = VectorParam.Process([], "processes to run")
171
172 dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
173 itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
174 if buildEnv['TARGET_ISA'] == 'sparc':
175 interrupts = VectorParam.SparcInterrupts(
176 [], "Interrupt Controller")
177 isa = VectorParam.SparcISA([], "ISA instance")
178 elif buildEnv['TARGET_ISA'] == 'alpha':
179 interrupts = VectorParam.AlphaInterrupts(
180 [], "Interrupt Controller")
181 isa = VectorParam.AlphaISA([], "ISA instance")
182 elif buildEnv['TARGET_ISA'] == 'x86':
183 interrupts = VectorParam.X86LocalApic([], "Interrupt Controller")
184 isa = VectorParam.X86ISA([], "ISA instance")
185 elif buildEnv['TARGET_ISA'] == 'mips':
186 interrupts = VectorParam.MipsInterrupts(
187 [], "Interrupt Controller")
188 isa = VectorParam.MipsISA([], "ISA instance")
189 elif buildEnv['TARGET_ISA'] == 'arm':
190 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
191 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
192 interrupts = VectorParam.ArmInterrupts(
193 [], "Interrupt Controller")
194 isa = VectorParam.ArmISA([], "ISA instance")
195 elif buildEnv['TARGET_ISA'] == 'power':
196 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
197 interrupts = VectorParam.PowerInterrupts(
198 [], "Interrupt Controller")
199 isa = VectorParam.PowerISA([], "ISA instance")
200 elif buildEnv['TARGET_ISA'] == 'riscv':
201 interrupts = VectorParam.RiscvInterrupts(
202 [], "Interrupt Controller")
203 isa = VectorParam.RiscvISA([], "ISA instance")
204 else:
205 print("Don't know what TLB to use for ISA %s" %
206 buildEnv['TARGET_ISA'])
207 sys.exit(1)
208
209 max_insts_all_threads = Param.Counter(0,
210 "terminate when all threads have reached this inst count")
211 max_insts_any_thread = Param.Counter(0,
212 "terminate when any thread reaches this inst count")
213 simpoint_start_insts = VectorParam.Counter([],
214 "starting instruction counts of simpoints")
215 max_loads_all_threads = Param.Counter(0,

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235 _uncached_slave_ports = []
236 _uncached_master_ports = []
237 if buildEnv['TARGET_ISA'] == 'x86':
238 _uncached_slave_ports += ["interrupts[0].pio",
239 "interrupts[0].int_slave"]
240 _uncached_master_ports += ["interrupts[0].int_master"]
241
242 def createInterruptController(self):
243 if buildEnv['TARGET_ISA'] == 'sparc':
244 self.interrupts = [SparcInterrupts() for i in range(self.numThreads)]
245 elif buildEnv['TARGET_ISA'] == 'alpha':
246 self.interrupts = [AlphaInterrupts() for i in range(self.numThreads)]
247 elif buildEnv['TARGET_ISA'] == 'x86':
248 self.interrupts = [X86LocalApic() for i in range(self.numThreads)]
249 elif buildEnv['TARGET_ISA'] == 'mips':
250 self.interrupts = [MipsInterrupts() for i in range(self.numThreads)]
251 elif buildEnv['TARGET_ISA'] == 'arm':
252 self.interrupts = [ArmInterrupts() for i in range(self.numThreads)]
253 elif buildEnv['TARGET_ISA'] == 'power':
254 self.interrupts = [PowerInterrupts() for i in range(self.numThreads)]
255 elif buildEnv['TARGET_ISA'] == 'riscv':
256 self.interrupts = \
257 [RiscvInterrupts() for i in range(self.numThreads)]
258 else:
259 print("Don't know what Interrupt Controller to use for ISA %s" %
260 buildEnv['TARGET_ISA'])
261 sys.exit(1)
262
263 def connectCachedPorts(self, bus):
264 for p in self._cached_ports:
265 exec('self.%s = bus.slave' % p)
266
267 def connectUncachedPorts(self, bus):
268 for p in self._uncached_slave_ports:
269 exec('self.%s = bus.master' % p)

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307 self.l2cache = l2c
308 self.toL2Bus.master = self.l2cache.cpu_side
309 self._cached_ports = ['l2cache.mem_side']
310
311 def createThreads(self):
312 # If no ISAs have been created, assume that the user wants the
313 # default ISA.
314 if len(self.isa) == 0:
315 self.isa = [ default_isa_class() for i in range(self.numThreads) ]
316 else:
317 if len(self.isa) != int(self.numThreads):
318 raise RuntimeError("Number of ISA instances doesn't "
319 "match thread count")
320 if self.checker != NULL:
321 self.checker.createThreads()
322
323 def addCheckerCpu(self):

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