1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# Copyright (c) 2011 Regents of the University of California
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;

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177 def addPrivateSplitL1Caches(self, ic, dc, iwc = None, dwc = None):
178 assert(len(self._cached_ports) < 7)
179 self.icache = ic
180 self.dcache = dc
181 self.icache_port = ic.cpu_side
182 self.dcache_port = dc.cpu_side
183 self._cached_ports = ['icache.mem_side', 'dcache.mem_side']
184 if buildEnv['FULL_SYSTEM']:
185 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
186 if iwc and dwc:
187 self.itb_walker_cache = iwc
188 self.dtb_walker_cache = dwc
189 self.itb.walker.port = iwc.cpu_side
190 self.dtb.walker.port = dwc.cpu_side
191 self._cached_ports += ["itb_walker_cache.mem_side", \
192 "dtb_walker_cache.mem_side"]
193 else:
194 self._cached_ports += ["itb.walker.port", "dtb.walker.port"]
195
196 def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
197 self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
198 self.toL2Bus = Bus()
199 self.connectCachedPorts(self.toL2Bus)
200 self.l2cache = l2c
201 self.l2cache.cpu_side = self.toL2Bus.port
202 self._cached_ports = ['l2cache.mem_side']