1# Copyright (c) 2005-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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109 Param.X86LocalApic(_localApic, "Interrupt Controller")
110 elif buildEnv['TARGET_ISA'] == 'mips':
111 dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
112 itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
113 if buildEnv['FULL_SYSTEM']:
114 interrupts = Param.MipsInterrupts(
115 MipsInterrupts(), "Interrupt Controller")
116 elif buildEnv['TARGET_ISA'] == 'arm':
117 dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
118 itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
119 if buildEnv['FULL_SYSTEM']:
120 interrupts = Param.ArmInterrupts(
121 ArmInterrupts(), "Interrupt Controller")
122 elif buildEnv['TARGET_ISA'] == 'power':
123 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
124 dtb = Param.PowerTLB(PowerTLB(), "Data TLB")

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152
153 _mem_ports = []
154 if buildEnv['TARGET_ISA'] == 'x86' and buildEnv['FULL_SYSTEM']:
155 _mem_ports = ["itb.walker.port",
156 "dtb.walker.port",
157 "interrupts.pio",
158 "interrupts.int_port"]
159
160 if buildEnv['TARGET_ISA'] == 'arm' and buildEnv['FULL_SYSTEM']:
161 _mem_ports = ["itb.walker.port",
162 "dtb.walker.port"]
163
164 def connectMemPorts(self, bus):
165 for p in self._mem_ports:
166 if p != 'physmem_port':
167 exec('self.%s = bus.port' % p)
168
169 def addPrivateSplitL1Caches(self, ic, dc):
170 assert(len(self._mem_ports) < 6)
171 self.icache = ic
172 self.dcache = dc
173 self.icache_port = ic.cpu_side
174 self.dcache_port = dc.cpu_side
175 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
176 if buildEnv['FULL_SYSTEM']:
177 if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
178 self._mem_ports += ["itb.walker.port", "dtb.walker.port"]
179
180 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
181 self.addPrivateSplitL1Caches(ic, dc)
182 self.toL2Bus = Bus()
183 self.connectMemPorts(self.toL2Bus)
184 self.l2cache = l2c
185 self.l2cache.cpu_side = self.toL2Bus.port
186 self._mem_ports = ['l2cache.mem_side']

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