1# Copyright (c) 2005-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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39
40if build_env['TARGET_ISA'] == 'alpha':
41 from AlphaTLB import AlphaDTB, AlphaITB
42elif build_env['TARGET_ISA'] == 'sparc':
43 from SparcTLB import SparcDTB, SparcITB
44elif build_env['TARGET_ISA'] == 'x86':
45 from X86TLB import X86DTB, X86ITB
46elif build_env['TARGET_ISA'] == 'mips':
47 from MipsTLB import MipsDTB, MipsITB
48
49class BaseCPU(SimObject):
50 type = 'BaseCPU'
51 abstract = True
52
53 system = Param.System(Parent.any, "system object")
54 cpu_id = Param.Int("CPU identifier")
55

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67 itb = Param.SparcITB(SparcITB(), "Instruction TLB")
68 elif build_env['TARGET_ISA'] == 'alpha':
69 dtb = Param.AlphaDTB(AlphaDTB(), "Data TLB")
70 itb = Param.AlphaITB(AlphaITB(), "Instruction TLB")
71 elif build_env['TARGET_ISA'] == 'x86':
72 dtb = Param.X86DTB(X86DTB(), "Data TLB")
73 itb = Param.X86ITB(X86ITB(), "Instruction TLB")
74 elif build_env['TARGET_ISA'] == 'mips':
75 dtb = Param.MipsDTB(MipsDTB(), "Data TLB")
76 itb = Param.MipsITB(MipsITB(), "Instruction TLB")
77 else:
78 print "Don't know what TLB to use for ISA %s" % \
79 build_env['TARGET_ISA']
80 sys.exit(1)
81
82 max_insts_all_threads = Param.Counter(0,
83 "terminate when all threads have reached this inst count")
84 max_insts_any_thread = Param.Counter(0,

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95
96 clock = Param.Clock('1t', "clock speed")
97 phase = Param.Latency('0ns', "clock phase")
98
99 tracer = Param.InstTracer(default_tracer, "Instruction tracer")
100
101 _mem_ports = []
102
103 if build_env['TARGET_ISA'] == 'x86':
104 itb.walker_port = Port("ITB page table walker port")
105 dtb.walker_port = Port("ITB page table walker port")
106 _mem_ports = ["itb.walker_port", "dtb.walker_port"]
107
108 def connectMemPorts(self, bus):
109 for p in self._mem_ports:
110 if p != 'physmem_port':
111 exec('self.%s = bus.port' % p)
112
113 def addPrivateSplitL1Caches(self, ic, dc):
114 assert(len(self._mem_ports) < 6)
115 self.icache = ic
116 self.dcache = dc
117 self.icache_port = ic.cpu_side
118 self.dcache_port = dc.cpu_side
119 self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
120 if build_env['TARGET_ISA'] == 'x86':
121 self._mem_ports += ["itb.walker_port", "dtb.walker_port"]
122
123 def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
124 self.addPrivateSplitL1Caches(ic, dc)
125 self.toL2Bus = Bus()
126 self.connectMemPorts(self.toL2Bus)
127 self.l2cache = l2c
128 self.l2cache.cpu_side = self.toL2Bus.port
129 self._mem_ports = ['l2cache.mem_side']