1# Copyright (c) 2012-2013, 2015-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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59from m5.objects.SubSystem import SubSystem
60from m5.objects.ClockDomain import *
61from m5.objects.Platform import Platform
62
63default_tracer = ExeTracer()
64
65if buildEnv['TARGET_ISA'] == 'alpha':
66 from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
67 from m5.objects.AlphaInterrupts import AlphaInterrupts as ArchInterrupts
68 from m5.objects.AlphaISA import AlphaISA as ArchISA
69 ArchInterruptsParam = VectorParam.AlphaInterrupts
70 ArchISAsParam = VectorParam.AlphaISA
71elif buildEnv['TARGET_ISA'] == 'sparc':
72 from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
73 from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
74 from m5.objects.SparcISA import SparcISA as ArchISA
75 ArchInterruptsParam = VectorParam.SparcInterrupts
76 ArchISAsParam = VectorParam.SparcISA
77elif buildEnv['TARGET_ISA'] == 'x86':
78 from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
79 from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
80 from m5.objects.X86ISA import X86ISA as ArchISA
81 ArchInterruptsParam = VectorParam.X86LocalApic
82 ArchISAsParam = VectorParam.X86ISA
83elif buildEnv['TARGET_ISA'] == 'mips':
84 from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
85 from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
86 from m5.objects.MipsISA import MipsISA as ArchISA
87 ArchInterruptsParam = VectorParam.MipsInterrupts
88 ArchISAsParam = VectorParam.MipsISA
89elif buildEnv['TARGET_ISA'] == 'arm':
90 from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
91 from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
92 from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
93 from m5.objects.ArmISA import ArmISA as ArchISA
94 ArchInterruptsParam = VectorParam.ArmInterrupts
95 ArchISAsParam = VectorParam.ArmISA
96elif buildEnv['TARGET_ISA'] == 'power':
97 from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
98 from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
99 from m5.objects.PowerISA import PowerISA as ArchISA
100 ArchInterruptsParam = VectorParam.PowerInterrupts
101 ArchISAsParam = VectorParam.PowerISA
102elif buildEnv['TARGET_ISA'] == 'riscv':
103 from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
104 from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
105 from m5.objects.RiscvISA import RiscvISA as ArchISA
106 ArchInterruptsParam = VectorParam.RiscvInterrupts
107 ArchISAsParam = VectorParam.RiscvISA
108else:
109 print("Don't know what object types to use for ISA %s" %
110 buildEnv['TARGET_ISA'])
111 sys.exit(1)
112
113class BaseCPU(ClockedObject):
114 type = 'BaseCPU'
115 abstract = True
116 cxx_header = "cpu/base.hh"
117
118 cxx_exports = [
119 PyBindMethod("switchOut"),

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177
178 wait_for_remote_gdb = Param.Bool(False,
179 "Wait for a remote GDB connection");
180
181 workload = VectorParam.Process([], "processes to run")
182
183 dtb = Param.BaseTLB(ArchDTB(), "Data TLB")
184 itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
185 if buildEnv['TARGET_ISA'] == 'arm':
186 istage2_mmu = Param.ArmStage2MMU(ArmStage2IMMU(), "Stage 2 trans")
187 dstage2_mmu = Param.ArmStage2MMU(ArmStage2DMMU(), "Stage 2 trans")
188 elif buildEnv['TARGET_ISA'] == 'power':
189 UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
190 interrupts = ArchInterruptsParam([], "Interrupt Controller")
191 isa = ArchISAsParam([], "ISA instance")
192
193 max_insts_all_threads = Param.Counter(0,
194 "terminate when all threads have reached this inst count")
195 max_insts_any_thread = Param.Counter(0,
196 "terminate when any thread reaches this inst count")
197 simpoint_start_insts = VectorParam.Counter([],
198 "starting instruction counts of simpoints")
199 max_loads_all_threads = Param.Counter(0,

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219 _uncached_slave_ports = []
220 _uncached_master_ports = []
221 if buildEnv['TARGET_ISA'] == 'x86':
222 _uncached_slave_ports += ["interrupts[0].pio",
223 "interrupts[0].int_slave"]
224 _uncached_master_ports += ["interrupts[0].int_master"]
225
226 def createInterruptController(self):
227 self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
228
229 def connectCachedPorts(self, bus):
230 for p in self._cached_ports:
231 exec('self.%s = bus.slave' % p)
232
233 def connectUncachedPorts(self, bus):
234 for p in self._uncached_slave_ports:
235 exec('self.%s = bus.master' % p)

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273 self.l2cache = l2c
274 self.toL2Bus.master = self.l2cache.cpu_side
275 self._cached_ports = ['l2cache.mem_side']
276
277 def createThreads(self):
278 # If no ISAs have been created, assume that the user wants the
279 # default ISA.
280 if len(self.isa) == 0:
281 self.isa = [ ArchISA() for i in range(self.numThreads) ]
282 else:
283 if len(self.isa) != int(self.numThreads):
284 raise RuntimeError("Number of ISA instances doesn't "
285 "match thread count")
286 if self.checker != NULL:
287 self.checker.createThreads()
288
289 def addCheckerCpu(self):

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