utility.hh (4120:3e09b5d32c45) utility.hh (4148:990c4663ce96)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_UTILITY_HH__
59#define __ARCH_X86_UTILITY_HH__
60
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_UTILITY_HH__
59#define __ARCH_X86_UTILITY_HH__
60
61#error X86 is not yet supported!
61#include "arch/x86/types.hh"
62#include "base/misc.hh"
62
63
64class ThreadContext;
65
63namespace X86ISA
64{
66namespace X86ISA
67{
68 static inline bool
69 inUserMode(ThreadContext *tc)
70 {
71 return false;
72 }
73
74 inline ExtMachInst
75 makeExtMI(MachInst inst, ThreadContext * xc) {
76 return inst;
77 }
78
79 inline bool isCallerSaveIntegerRegister(unsigned int reg) {
80 panic("register classification not implemented");
81 return false;
82 }
83
84 inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
85 panic("register classification not implemented");
86 return false;
87 }
88
89 inline bool isCallerSaveFloatRegister(unsigned int reg) {
90 panic("register classification not implemented");
91 return false;
92 }
93
94 inline bool isCalleeSaveFloatRegister(unsigned int reg) {
95 panic("register classification not implemented");
96 return false;
97 }
98
99 // Instruction address compression hooks
100 inline Addr realPCToFetchPC(const Addr &addr)
101 {
102 return addr;
103 }
104
105 inline Addr fetchPCToRealPC(const Addr &addr)
106 {
107 return addr;
108 }
109
110 // the size of "fetched" instructions (not necessarily the size
111 // of real instructions for PISA)
112 inline size_t fetchInstSize()
113 {
114 return sizeof(MachInst);
115 }
116
117 /**
118 * Function to insure ISA semantics about 0 registers.
119 * @param tc The thread context.
120 */
121 template <class TC>
122 void zeroRegisters(TC *tc);
123
124 inline void initCPU(ThreadContext *tc, int cpuId)
125 {
126 panic("initCPU not implemented!\n");
127 }
65};
66
67#endif // __ARCH_X86_UTILITY_HH__
128};
129
130#endif // __ARCH_X86_UTILITY_HH__