utility.hh (10417:710ee116eb68) utility.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_UTILITY_HH__
41#define __ARCH_X86_UTILITY_HH__
42
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/types.hh"
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_X86_UTILITY_HH__
41#define __ARCH_X86_UTILITY_HH__
42
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/types.hh"
45#include "base/hashmap.hh"
46#include "base/misc.hh"
47#include "base/types.hh"
48#include "cpu/static_inst.hh"
49#include "cpu/thread_context.hh"
50#include "sim/full_system.hh"
51
52class ThreadContext;
53
54namespace X86ISA
55{
56
57 inline PCState
58 buildRetPC(const PCState &curPC, const PCState &callPC)
59 {
60 PCState retPC = callPC;
61 retPC.uEnd();
62 return retPC;
63 }
64
65 uint64_t
66 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
67
68 static inline bool
69 inUserMode(ThreadContext *tc)
70 {
71 if (!FullSystem) {
72 return true;
73 } else {
74 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
75 return m5reg.cpl == 3;
76 }
77 }
78
79 /**
80 * Function to insure ISA semantics about 0 registers.
81 * @param tc The thread context.
82 */
83 template <class TC>
84 void zeroRegisters(TC *tc);
85
86 void initCPU(ThreadContext *tc, int cpuId);
87
88 void startupCPU(ThreadContext *tc, int cpuId);
89
90 void copyRegs(ThreadContext *src, ThreadContext *dest);
91
92 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
93
94 void skipFunction(ThreadContext *tc);
95
96 inline void
97 advancePC(PCState &pc, const StaticInstPtr &inst)
98 {
99 inst->advancePC(pc);
100 }
101
102 inline uint64_t
103 getExecutingAsid(ThreadContext *tc)
104 {
105 return 0;
106 }
107
108
109 /**
110 * Reconstruct the rflags register from the internal gem5 register
111 * state.
112 *
113 * gem5 stores rflags in several different registers to avoid
114 * pipeline dependencies. In order to get the true rflags value,
115 * we can't simply read the value of MISCREG_RFLAGS. Instead, we
116 * need to read out various state from microcode registers and
117 * merge that with MISCREG_RFLAGS.
118 *
119 * @param tc Thread context to read rflags from.
120 * @return rflags as seen by the guest.
121 */
122 uint64_t getRFlags(ThreadContext *tc);
123
124 /**
125 * Set update the rflags register and internal gem5 state.
126 *
127 * @note This function does not update MISCREG_M5_REG. You might
128 * need to update this register by writing anything to
129 * MISCREG_M5_REG with side-effects.
130 *
131 * @see X86ISA::getRFlags()
132 *
133 * @param tc Thread context to update
134 * @param val New rflags value to store in TC
135 */
136 void setRFlags(ThreadContext *tc, uint64_t val);
137
138 /**
139 * Extract the bit string representing a double value.
140 */
141 inline uint64_t getDoubleBits(double val) {
142 return *(uint64_t *)(&val);
143 }
144
145 /**
146 * Convert an x87 tag word to abridged tag format.
147 *
148 * Convert from the x87 tag representation to the tag abridged
149 * representation used in the FXSAVE area. The classic format uses
150 * 2 bits per stack position to indicate if a position is valid,
151 * zero, special, or empty. The abridged format only stores
152 * whether a position is empty or not.
153 *
154 * @param ftw Tag word in classic x87 format.
155 * @return Tag word in the abridged format.
156 */
157 uint8_t convX87TagsToXTags(uint16_t ftw);
158
159 /**
160 * Convert an x87 xtag word to normal tags format.
161 *
162 * Convert from the abridged x87 tag representation used in the
163 * FXSAVE area to a full x87 tag. The classic format uses 2 bits
164 * per stack position to indicate if a position is valid, zero,
165 * special, or empty. The abridged format only stores whether a
166 * position is empty or not.
167 *
168 * @todo Reconstruct the correct state of stack positions instead
169 * of just valid/invalid.
170 *
171 * @param ftwx Tag word in the abridged format.
172 * @return Tag word in classic x87 format.
173 */
174 uint16_t convX87XTagsToTags(uint8_t ftwx);
175
176 /**
177 * Generate and updated x87 tag register after a push/pop
178 * operation.
179 *
180 * @note There is currently no support for setting other tags than
181 * valid and invalid. A real x87 will set the tag value to zero or
182 * special for some special floating point values.
183 *
184 * @param ftw Current value of the FTW register.
185 * @param top Current x87 TOP value.
186 * @param spm Stack displacement.
187 * @return New value of the FTW register.
188 */
189 uint16_t genX87Tags(uint16_t ftw, uint8_t top, int8_t spm);
190
191 /**
192 * Load an 80-bit float from memory and convert it to double.
193 *
194 * @param mem Pointer to an 80-bit float.
195 * @return double representation of the 80-bit float.
196 */
197 double loadFloat80(const void *mem);
198
199 /**
200 * Convert and store a double as an 80-bit float.
201 *
202 * @param mem Pointer to destination for the 80-bit float.
203 * @param value Double precision float to store.
204 */
205 void storeFloat80(void *mem, double value);
206}
207
208#endif // __ARCH_X86_UTILITY_HH__
45#include "base/misc.hh"
46#include "base/types.hh"
47#include "cpu/static_inst.hh"
48#include "cpu/thread_context.hh"
49#include "sim/full_system.hh"
50
51class ThreadContext;
52
53namespace X86ISA
54{
55
56 inline PCState
57 buildRetPC(const PCState &curPC, const PCState &callPC)
58 {
59 PCState retPC = callPC;
60 retPC.uEnd();
61 return retPC;
62 }
63
64 uint64_t
65 getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
66
67 static inline bool
68 inUserMode(ThreadContext *tc)
69 {
70 if (!FullSystem) {
71 return true;
72 } else {
73 HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
74 return m5reg.cpl == 3;
75 }
76 }
77
78 /**
79 * Function to insure ISA semantics about 0 registers.
80 * @param tc The thread context.
81 */
82 template <class TC>
83 void zeroRegisters(TC *tc);
84
85 void initCPU(ThreadContext *tc, int cpuId);
86
87 void startupCPU(ThreadContext *tc, int cpuId);
88
89 void copyRegs(ThreadContext *src, ThreadContext *dest);
90
91 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
92
93 void skipFunction(ThreadContext *tc);
94
95 inline void
96 advancePC(PCState &pc, const StaticInstPtr &inst)
97 {
98 inst->advancePC(pc);
99 }
100
101 inline uint64_t
102 getExecutingAsid(ThreadContext *tc)
103 {
104 return 0;
105 }
106
107
108 /**
109 * Reconstruct the rflags register from the internal gem5 register
110 * state.
111 *
112 * gem5 stores rflags in several different registers to avoid
113 * pipeline dependencies. In order to get the true rflags value,
114 * we can't simply read the value of MISCREG_RFLAGS. Instead, we
115 * need to read out various state from microcode registers and
116 * merge that with MISCREG_RFLAGS.
117 *
118 * @param tc Thread context to read rflags from.
119 * @return rflags as seen by the guest.
120 */
121 uint64_t getRFlags(ThreadContext *tc);
122
123 /**
124 * Set update the rflags register and internal gem5 state.
125 *
126 * @note This function does not update MISCREG_M5_REG. You might
127 * need to update this register by writing anything to
128 * MISCREG_M5_REG with side-effects.
129 *
130 * @see X86ISA::getRFlags()
131 *
132 * @param tc Thread context to update
133 * @param val New rflags value to store in TC
134 */
135 void setRFlags(ThreadContext *tc, uint64_t val);
136
137 /**
138 * Extract the bit string representing a double value.
139 */
140 inline uint64_t getDoubleBits(double val) {
141 return *(uint64_t *)(&val);
142 }
143
144 /**
145 * Convert an x87 tag word to abridged tag format.
146 *
147 * Convert from the x87 tag representation to the tag abridged
148 * representation used in the FXSAVE area. The classic format uses
149 * 2 bits per stack position to indicate if a position is valid,
150 * zero, special, or empty. The abridged format only stores
151 * whether a position is empty or not.
152 *
153 * @param ftw Tag word in classic x87 format.
154 * @return Tag word in the abridged format.
155 */
156 uint8_t convX87TagsToXTags(uint16_t ftw);
157
158 /**
159 * Convert an x87 xtag word to normal tags format.
160 *
161 * Convert from the abridged x87 tag representation used in the
162 * FXSAVE area to a full x87 tag. The classic format uses 2 bits
163 * per stack position to indicate if a position is valid, zero,
164 * special, or empty. The abridged format only stores whether a
165 * position is empty or not.
166 *
167 * @todo Reconstruct the correct state of stack positions instead
168 * of just valid/invalid.
169 *
170 * @param ftwx Tag word in the abridged format.
171 * @return Tag word in classic x87 format.
172 */
173 uint16_t convX87XTagsToTags(uint8_t ftwx);
174
175 /**
176 * Generate and updated x87 tag register after a push/pop
177 * operation.
178 *
179 * @note There is currently no support for setting other tags than
180 * valid and invalid. A real x87 will set the tag value to zero or
181 * special for some special floating point values.
182 *
183 * @param ftw Current value of the FTW register.
184 * @param top Current x87 TOP value.
185 * @param spm Stack displacement.
186 * @return New value of the FTW register.
187 */
188 uint16_t genX87Tags(uint16_t ftw, uint8_t top, int8_t spm);
189
190 /**
191 * Load an 80-bit float from memory and convert it to double.
192 *
193 * @param mem Pointer to an 80-bit float.
194 * @return double representation of the 80-bit float.
195 */
196 double loadFloat80(const void *mem);
197
198 /**
199 * Convert and store a double as an 80-bit float.
200 *
201 * @param mem Pointer to destination for the 80-bit float.
202 * @param value Double precision float to store.
203 */
204 void storeFloat80(void *mem, double value);
205}
206
207#endif // __ARCH_X86_UTILITY_HH__