utility.cc (9751:e039a48eeb99) | utility.cc (9759:8f1f1bdedf8c) |
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1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * Copyright (c) 2011 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 222 unchanged lines hidden (view full) --- 231} 232 233void 234skipFunction(ThreadContext *tc) 235{ 236 panic("Not implemented for x86\n"); 237} 238 | 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * Copyright (c) 2011 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating --- 222 unchanged lines hidden (view full) --- 231} 232 233void 234skipFunction(ThreadContext *tc) 235{ 236 panic("Not implemented for x86\n"); 237} 238 |
239uint64_t 240getRFlags(ThreadContext *tc) 241{ 242 const uint64_t ncc_flags(tc->readMiscRegNoEffect(MISCREG_RFLAGS)); 243 const uint64_t cc_flags(tc->readIntReg(X86ISA::INTREG_PSEUDO(0))); 244 const uint64_t cfof_bits(tc->readIntReg(X86ISA::INTREG_PSEUDO(1))); 245 const uint64_t df_bit(tc->readIntReg(X86ISA::INTREG_PSEUDO(2))); 246 // ecf (PSEUDO(3)) & ezf (PSEUDO(4)) are only visible to 247 // microcode, so we can safely ignore them. |
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239 | 248 |
249 // Reconstruct the real rflags state, mask out internal flags, and 250 // make sure reserved bits have the expected values. 251 return ((ncc_flags | cc_flags | cfof_bits | df_bit) & 0x3F7FD5) 252 | 0x2; 253} 254 255void 256setRFlags(ThreadContext *tc, uint64_t val) 257{ 258 tc->setIntReg(X86ISA::INTREG_PSEUDO(0), val & ccFlagMask); 259 tc->setIntReg(X86ISA::INTREG_PSEUDO(1), val & cfofMask); 260 tc->setIntReg(X86ISA::INTREG_PSEUDO(2), val & DFBit); 261 262 // Internal microcode registers (ECF & EZF) 263 tc->setIntReg(X86ISA::INTREG_PSEUDO(3), 0); 264 tc->setIntReg(X86ISA::INTREG_PSEUDO(4), 0); 265 266 // Update the RFLAGS misc reg with whatever didn't go into the 267 // magic registers. 268 tc->setMiscReg(MISCREG_RFLAGS, val & ~(ccFlagMask | cfofMask | DFBit)); 269} 270 |
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240} // namespace X86_ISA | 271} // namespace X86_ISA |