utility.cc (8466:9c754e3022b7) utility.cc (8768:314eb1e2fa94)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2011 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 24 unchanged lines hidden (view full) ---

33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * Copyright (c) 2011 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 24 unchanged lines hidden (view full) ---

33 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
34 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
35 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 *
38 * Authors: Gabe Black
39 */
40
41#include "config/full_system.hh"
42
43#if FULL_SYSTEM
44#include "arch/x86/interrupts.hh"
41#include "arch/x86/interrupts.hh"
45#endif
46#include "arch/x86/registers.hh"
47#include "arch/x86/tlb.hh"
48#include "arch/x86/utility.hh"
49#include "arch/x86/x86_traits.hh"
50#include "cpu/base.hh"
51#include "sim/system.hh"
52
53namespace X86ISA {
54
55uint64_t
56getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
57{
42#include "arch/x86/registers.hh"
43#include "arch/x86/tlb.hh"
44#include "arch/x86/utility.hh"
45#include "arch/x86/x86_traits.hh"
46#include "cpu/base.hh"
47#include "sim/system.hh"
48
49namespace X86ISA {
50
51uint64_t
52getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
53{
58#if FULL_SYSTEM
59 panic("getArgument() not implemented for x86!\n");
54 panic("getArgument() not implemented for x86!\n");
60#else
61 panic("getArgument() only implemented for FULL_SYSTEM\n");
62 M5_DUMMY_RETURN
55 M5_DUMMY_RETURN
63#endif
64}
65
56}
57
66# if FULL_SYSTEM
67void initCPU(ThreadContext *tc, int cpuId)
68{
69 // This function is essentially performing a reset. The actual INIT
70 // interrupt does a subset of this, so we'll piggyback on some of its
71 // functionality.
72 InitInterrupt init(0);
73 init.invoke(tc);
74

--- 113 unchanged lines hidden (view full) ---

188 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
189
190 tc->setMiscReg(MISCREG_VM_CR, 0);
191 tc->setMiscReg(MISCREG_IGNNE, 0);
192 tc->setMiscReg(MISCREG_SMM_CTL, 0);
193 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
194}
195
58void initCPU(ThreadContext *tc, int cpuId)
59{
60 // This function is essentially performing a reset. The actual INIT
61 // interrupt does a subset of this, so we'll piggyback on some of its
62 // functionality.
63 InitInterrupt init(0);
64 init.invoke(tc);
65

--- 113 unchanged lines hidden (view full) ---

179 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
180
181 tc->setMiscReg(MISCREG_VM_CR, 0);
182 tc->setMiscReg(MISCREG_IGNNE, 0);
183 tc->setMiscReg(MISCREG_SMM_CTL, 0);
184 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
185}
186
196#endif
197
198void startupCPU(ThreadContext *tc, int cpuId)
199{
187void startupCPU(ThreadContext *tc, int cpuId)
188{
200#if FULL_SYSTEM
201 if (cpuId == 0) {
189 if (cpuId == 0 || !FullSystem) {
202 tc->activate(0);
203 } else {
204 // This is an application processor (AP). It should be initialized to
205 // look like only the BIOS POST has run on it and put then put it into
206 // a halted state.
207 tc->suspend(0);
208 }
190 tc->activate(0);
191 } else {
192 // This is an application processor (AP). It should be initialized to
193 // look like only the BIOS POST has run on it and put then put it into
194 // a halted state.
195 tc->suspend(0);
196 }
209#else
210 tc->activate(0);
211#endif
212}
213
214void
215copyMiscRegs(ThreadContext *src, ThreadContext *dest)
216{
217 // This function assumes no side effects other than TLB invalidation
218 // need to be considered while copying state. That will likely not be
219 // true in the future.

--- 34 unchanged lines hidden --- 		197}
198
199void
200copyMiscRegs(ThreadContext *src, ThreadContext *dest)
201{
202 // This function assumes no side effects other than TLB invalidation
203 // need to be considered while copying state. That will likely not be
204 // true in the future.

--- 34 unchanged lines hidden ---