utility.cc (6042:827bd9f03fdc) utility.cc (6048:65a321a3a691)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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77 panic("getArgument() only implemented for FULL_SYSTEM\n");
78 M5_DUMMY_RETURN
79#endif
80}
81
82# if FULL_SYSTEM
83void initCPU(ThreadContext *tc, int cpuId)
84{
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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77 panic("getArgument() only implemented for FULL_SYSTEM\n");
78 M5_DUMMY_RETURN
79#endif
80}
81
82# if FULL_SYSTEM
83void initCPU(ThreadContext *tc, int cpuId)
84{
85 // The otherwise unmodified integer registers should be set to 0.
86 for (int index = 0; index < NUM_INTREGS; index++) {
87 tc->setIntReg(index, 0);
88 }
85 // This function is essentially performing a reset. The actual INIT
86 // interrupt does a subset of this, so we'll piggyback on some of its
87 // functionality.
88 InitInterrupt init(0);
89 init.invoke(tc);
89
90
91 tc->setMicroPC(0);
92 tc->setNextMicroPC(1);
93
90 // These next two loops zero internal microcode and implicit registers.
91 // They aren't specified by the ISA but are used internally by M5's
92 // implementation.
93 for (int index = 0; index < NumMicroIntRegs; index++) {
94 tc->setIntReg(INTREG_MICRO(index), 0);
95 }
96
97 for (int index = 0; index < NumImplicitIntRegs; index++) {
98 tc->setIntReg(INTREG_IMPLICIT(index), 0);
99 }
100
101 // Set integer register EAX to 0 to indicate that the optional BIST
102 // passed. No BIST actually runs, but software may still check this
103 // register for errors.
104 tc->setIntReg(INTREG_RAX, 0);
105
94 // These next two loops zero internal microcode and implicit registers.
95 // They aren't specified by the ISA but are used internally by M5's
96 // implementation.
97 for (int index = 0; index < NumMicroIntRegs; index++) {
98 tc->setIntReg(INTREG_MICRO(index), 0);
99 }
100
101 for (int index = 0; index < NumImplicitIntRegs; index++) {
102 tc->setIntReg(INTREG_IMPLICIT(index), 0);
103 }
104
105 // Set integer register EAX to 0 to indicate that the optional BIST
106 // passed. No BIST actually runs, but software may still check this
107 // register for errors.
108 tc->setIntReg(INTREG_RAX, 0);
109
106 //The following values are dictated by the architecture for after a RESET#
107 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
110 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
108 tc->setMiscReg(MISCREG_CR2, 0);
109 tc->setMiscReg(MISCREG_CR3, 0);
110 tc->setMiscReg(MISCREG_CR4, 0);
111 tc->setMiscReg(MISCREG_CR8, 0);
112
111 tc->setMiscReg(MISCREG_CR8, 0);
112
113 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
114
115 tc->setMiscReg(MISCREG_EFER, 0);
116
117 SegAttr dataAttr = 0;
118 dataAttr.writable = 1;
119 dataAttr.readable = 1;
120 dataAttr.expandDown = 0;
121 dataAttr.dpl = 0;
122 dataAttr.defaultSize = 0;
123
124 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
125 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
126 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
127 tc->setMiscReg(MISCREG_SEG_EFF_BASE(seg), 0);
128 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
129 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
130 }
131
132 SegAttr codeAttr = 0;
133 codeAttr.writable = 0;
134 codeAttr.readable = 1;
135 codeAttr.expandDown = 0;
136 codeAttr.dpl = 0;
137 codeAttr.defaultSize = 0;
138
139 tc->setMiscReg(MISCREG_CS, 0xf000);
140 tc->setMiscReg(MISCREG_CS_BASE,
141 0x00000000ffff0000ULL);
142 tc->setMiscReg(MISCREG_CS_EFF_BASE,
143 0x00000000ffff0000ULL);
144 // This has the base value pre-added.
145 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
146 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
147
148 tc->setPC(0x000000000000fff0ULL +
149 tc->readMiscReg(MISCREG_CS_BASE));
150 tc->setNextPC(tc->readPC() + sizeof(MachInst));
151
152 tc->setMiscReg(MISCREG_TSG_BASE, 0);
153 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
154
155 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
156 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
157
158 tc->setMiscReg(MISCREG_TSL, 0);
159 tc->setMiscReg(MISCREG_TSL_BASE, 0);
160 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
161 tc->setMiscReg(MISCREG_TSL_ATTR, 0);
162
163 tc->setMiscReg(MISCREG_TR, 0);
164 tc->setMiscReg(MISCREG_TR_BASE, 0);
165 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
166 tc->setMiscReg(MISCREG_TR_ATTR, 0);
167
168 // This value should be the family/model/stepping of the processor.
169 // (page 418). It should be consistent with the value from CPUID, but the
170 // actual value probably doesn't matter much.
171 tc->setIntReg(INTREG_RDX, 0);
172
173 // TODO initialize x87, 64 bit, and 128 bit media state
174
175 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
176 for (int i = 0; i < 8; i++) {
177 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
178 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
179 }
180 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);

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197
198 for (int i = 0; i < 5; i++) {
199 tc->setMiscReg(MISCREG_MC_CTL(i), 0);
200 tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
201 tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
202 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
203 }
204
113 // TODO initialize x87, 64 bit, and 128 bit media state
114
115 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
116 for (int i = 0; i < 8; i++) {
117 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
118 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
119 }
120 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);

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137
138 for (int i = 0; i < 5; i++) {
139 tc->setMiscReg(MISCREG_MC_CTL(i), 0);
140 tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
141 tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
142 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
143 }
144
205 tc->setMiscReg(MISCREG_DR0, 0);
206 tc->setMiscReg(MISCREG_DR1, 0);
207 tc->setMiscReg(MISCREG_DR2, 0);
208 tc->setMiscReg(MISCREG_DR3, 0);
209
210 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
211 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
212
213 tc->setMiscReg(MISCREG_TSC, 0);
214 tc->setMiscReg(MISCREG_TSC_AUX, 0);
215
216 for (int i = 0; i < 4; i++) {
217 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
218 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
219 }
220

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246 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
247 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
248 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
249 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
250 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
251
252 // Invalidate the caches (this should already be done for us)
253
145 tc->setMiscReg(MISCREG_TSC, 0);
146 tc->setMiscReg(MISCREG_TSC_AUX, 0);
147
148 for (int i = 0; i < 4; i++) {
149 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
150 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
151 }
152

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178 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
179 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
180 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
181 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
182 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
183
184 // Invalidate the caches (this should already be done for us)
185
254 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
255 // currently being handled at all.
256
257 LocalApicBase lApicBase = 0;
258 lApicBase.base = 0xFEE00000 >> 12;
259 lApicBase.enable = 1;
260 lApicBase.bsp = (cpuId == 0);
261 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
262
263 Interrupts * interrupts = dynamic_cast<Interrupts *>(
264 tc->getCpuPtr()->getInterruptController());

--- 35 unchanged lines hidden --- 		186 LocalApicBase lApicBase = 0;
187 lApicBase.base = 0xFEE00000 >> 12;
188 lApicBase.enable = 1;
189 lApicBase.bsp = (cpuId == 0);
190 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
191
192 Interrupts * interrupts = dynamic_cast<Interrupts *>(
193 tc->getCpuPtr()->getInterruptController());

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