utility.cc (5360:02a3af203516) utility.cc (5647:b06b49498c79)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "config/full_system.hh"
59
60#if FULL_SYSTEM
61#include "arch/x86/interrupts.hh"
62#endif
58#include "arch/x86/intregs.hh"
59#include "arch/x86/miscregs.hh"
60#include "arch/x86/segmentregs.hh"
61#include "arch/x86/utility.hh"
62#include "arch/x86/x86_traits.hh"
63#include "arch/x86/intregs.hh"
64#include "arch/x86/miscregs.hh"
65#include "arch/x86/segmentregs.hh"
66#include "arch/x86/utility.hh"
67#include "arch/x86/x86_traits.hh"
68#include "cpu/base.hh"
63#include "sim/system.hh"
64
65namespace X86ISA {
66
67uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
68#if FULL_SYSTEM
69 panic("getArgument() not implemented for x86!\n");
70#else

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249 // currently being handled at all.
250
251 LocalApicBase lApicBase = 0;
252 lApicBase.base = 0xFEE00000 >> 12;
253 lApicBase.enable = 1;
254 lApicBase.bsp = (cpuId == 0);
255 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
256
69#include "sim/system.hh"
70
71namespace X86ISA {
72
73uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
74#if FULL_SYSTEM
75 panic("getArgument() not implemented for x86!\n");
76#else

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255 // currently being handled at all.
256
257 LocalApicBase lApicBase = 0;
258 lApicBase.base = 0xFEE00000 >> 12;
259 lApicBase.enable = 1;
260 lApicBase.bsp = (cpuId == 0);
261 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
262
257 tc->setMiscRegNoEffect(MISCREG_APIC_ID, cpuId << 24);
263 Interrupts * interrupts = dynamic_cast<Interrupts *>(
264 tc->getCpuPtr()->getInterruptController());
265 assert(interrupts);
258
266
259 tc->setMiscRegNoEffect(MISCREG_APIC_VERSION, (5 << 16) | 0x14);
267 interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
260
268
269 interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
270
261 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
262
263 tc->setMiscReg(MISCREG_VM_CR, 0);
264 tc->setMiscReg(MISCREG_IGNNE, 0);
265 tc->setMiscReg(MISCREG_SMM_CTL, 0);
266 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
267}
268

--- 25 unchanged lines hidden --- 		271 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
272
273 tc->setMiscReg(MISCREG_VM_CR, 0);
274 tc->setMiscReg(MISCREG_IGNNE, 0);
275 tc->setMiscReg(MISCREG_SMM_CTL, 0);
276 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
277}
278

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