utility.cc (5289:ca5390e654b8) utility.cc (5294:7222bdaed33b)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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138 // This has the base value pre-added.
139 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
140 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
141
142 tc->setPC(0x000000000000fff0ULL +
143 tc->readMiscReg(MISCREG_CS_BASE));
144 tc->setNextPC(tc->readPC() + sizeof(MachInst));
145
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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138 // This has the base value pre-added.
139 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
140 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
141
142 tc->setPC(0x000000000000fff0ULL +
143 tc->readMiscReg(MISCREG_CS_BASE));
144 tc->setNextPC(tc->readPC() + sizeof(MachInst));
145
146 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
147 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
146 tc->setMiscReg(MISCREG_TSG_BASE, 0);
147 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xffff);
148
149 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
150 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
151
148
149 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
150 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
151
152 tc->setMiscReg(MISCREG_LDTR, 0);
153 tc->setMiscReg(MISCREG_LDTR_BASE, 0);
154 tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff);
155 tc->setMiscReg(MISCREG_LDTR_ATTR, 0);
152 tc->setMiscReg(MISCREG_TSL, 0);
153 tc->setMiscReg(MISCREG_TSL_BASE, 0);
154 tc->setMiscReg(MISCREG_TSL_LIMIT, 0xffff);
155 tc->setMiscReg(MISCREG_TSL_ATTR, 0);
156
157 tc->setMiscReg(MISCREG_TR, 0);
158 tc->setMiscReg(MISCREG_TR_BASE, 0);
159 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
160 tc->setMiscReg(MISCREG_TR_ATTR, 0);
161
162 // This value should be the family/model/stepping of the processor.
163 // (page 418). It should be consistent with the value from CPUID, but the

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301 csDesc.d = 0; // default operand size
302 //Because we're dealing with a pointer and I don't think it's
303 //guaranteed that there isn't anything in a nonvirtual class between
304 //it's beginning in memory and it's actual data, we'll use an
305 //intermediary.
306 uint64_t csDescVal = csDesc;
307 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
308
156
157 tc->setMiscReg(MISCREG_TR, 0);
158 tc->setMiscReg(MISCREG_TR_BASE, 0);
159 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
160 tc->setMiscReg(MISCREG_TR_ATTR, 0);
161
162 // This value should be the family/model/stepping of the processor.
163 // (page 418). It should be consistent with the value from CPUID, but the

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301 csDesc.d = 0; // default operand size
302 //Because we're dealing with a pointer and I don't think it's
303 //guaranteed that there isn't anything in a nonvirtual class between
304 //it's beginning in memory and it's actual data, we'll use an
305 //intermediary.
306 uint64_t csDescVal = csDesc;
307 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
308
309 tc->setMiscReg(MISCREG_GDTR_BASE, GDTBase);
310 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xF);
309 tc->setMiscReg(MISCREG_TSG_BASE, GDTBase);
310 tc->setMiscReg(MISCREG_TSG_LIMIT, 0xF);
311
312 /*
313 * Identity map the first 4GB of memory. In order to map this region
314 * of memory in long mode, there needs to be one actual page map level
315 * 4 entry which points to one page directory pointer table which
316 * points to 4 different page directory tables which are full of two
317 * megabyte pages. All of the other entries in valid tables are set
318 * to indicate that they don't pertain to anything valid and will

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312 /*
313 * Identity map the first 4GB of memory. In order to map this region
314 * of memory in long mode, there needs to be one actual page map level
315 * 4 entry which points to one page directory pointer table which
316 * points to 4 different page directory tables which are full of two
317 * megabyte pages. All of the other entries in valid tables are set
318 * to indicate that they don't pertain to anything valid and will

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