utility.cc (5234:55e0b1585b04) utility.cc (5264:f290df2f2261)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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93 }
94
95 // Set integer register EAX to 0 to indicate that the optional BIST
96 // passed. No BIST actually runs, but software may still check this
97 // register for errors.
98 tc->setIntReg(INTREG_RAX, 0);
99
100 //The following values are dictated by the architecture for after a RESET#
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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93 }
94
95 // Set integer register EAX to 0 to indicate that the optional BIST
96 // passed. No BIST actually runs, but software may still check this
97 // register for errors.
98 tc->setIntReg(INTREG_RAX, 0);
99
100 //The following values are dictated by the architecture for after a RESET#
101 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010);
101 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
102 tc->setMiscReg(MISCREG_CR2, 0);
103 tc->setMiscReg(MISCREG_CR3, 0);
104 tc->setMiscReg(MISCREG_CR4, 0);
105 tc->setMiscReg(MISCREG_CR8, 0);
106
102 tc->setMiscReg(MISCREG_CR2, 0);
103 tc->setMiscReg(MISCREG_CR3, 0);
104 tc->setMiscReg(MISCREG_CR4, 0);
105 tc->setMiscReg(MISCREG_CR8, 0);
106
107 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
107 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002ULL);
108
109 tc->setMiscReg(MISCREG_EFER, 0);
110
111 SegAttr dataAttr = 0;
112 dataAttr.writable = 1;
113 dataAttr.readable = 1;
114 dataAttr.expandDown = 0;
115 dataAttr.dpl = 0;

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125 SegAttr codeAttr = 0;
126 codeAttr.writable = 0;
127 codeAttr.readable = 1;
128 codeAttr.expandDown = 0;
129 codeAttr.dpl = 0;
130 codeAttr.defaultSize = 0;
131
132 tc->setMiscReg(MISCREG_CS, 0xf000);
108
109 tc->setMiscReg(MISCREG_EFER, 0);
110
111 SegAttr dataAttr = 0;
112 dataAttr.writable = 1;
113 dataAttr.readable = 1;
114 dataAttr.expandDown = 0;
115 dataAttr.dpl = 0;

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125 SegAttr codeAttr = 0;
126 codeAttr.writable = 0;
127 codeAttr.readable = 1;
128 codeAttr.expandDown = 0;
129 codeAttr.dpl = 0;
130 codeAttr.defaultSize = 0;
131
132 tc->setMiscReg(MISCREG_CS, 0xf000);
133 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
133 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000ULL);
134 // This has the base value pre-added.
135 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
136 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
137
134 // This has the base value pre-added.
135 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
136 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
137
138 tc->setPC(0x000000000000fff0 +
138 tc->setPC(0x000000000000fff0ULL +
139 tc->readMiscReg(MISCREG_CS_BASE));
140 tc->setNextPC(tc->readPC() + sizeof(MachInst));
141
142 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
143 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
144
145 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
146 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);

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192 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
193 }
194
195 tc->setMiscReg(MISCREG_DR0, 0);
196 tc->setMiscReg(MISCREG_DR1, 0);
197 tc->setMiscReg(MISCREG_DR2, 0);
198 tc->setMiscReg(MISCREG_DR3, 0);
199
139 tc->readMiscReg(MISCREG_CS_BASE));
140 tc->setNextPC(tc->readPC() + sizeof(MachInst));
141
142 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
143 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
144
145 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
146 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);

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192 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
193 }
194
195 tc->setMiscReg(MISCREG_DR0, 0);
196 tc->setMiscReg(MISCREG_DR1, 0);
197 tc->setMiscReg(MISCREG_DR2, 0);
198 tc->setMiscReg(MISCREG_DR3, 0);
199
200 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
201 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
200 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0ULL);
201 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400ULL);
202
203 tc->setMiscReg(MISCREG_TSC, 0);
204 tc->setMiscReg(MISCREG_TSC_AUX, 0);
205
206 for (int i = 0; i < 4; i++) {
207 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
208 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
209 }

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215 tc->setMiscReg(MISCREG_SF_MASK, 0);
216
217 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
218
219 tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
220 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
221 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
222
202
203 tc->setMiscReg(MISCREG_TSC, 0);
204 tc->setMiscReg(MISCREG_TSC_AUX, 0);
205
206 for (int i = 0; i < 4; i++) {
207 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
208 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
209 }

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215 tc->setMiscReg(MISCREG_SF_MASK, 0);
216
217 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
218
219 tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
220 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
221 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
222
223 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406);
223 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
224
225 tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
226
227 tc->setMiscReg(MISCREG_IORR_BASE0, 0);
228 tc->setMiscReg(MISCREG_IORR_BASE1, 0);
229
230 tc->setMiscReg(MISCREG_IORR_MASK0, 0);
231 tc->setMiscReg(MISCREG_IORR_MASK1, 0);

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225 tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
226
227 tc->setMiscReg(MISCREG_IORR_BASE0, 0);
228 tc->setMiscReg(MISCREG_IORR_BASE1, 0);
229
230 tc->setMiscReg(MISCREG_IORR_MASK0, 0);
231 tc->setMiscReg(MISCREG_IORR_MASK1, 0);

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