utility.cc (5135:6ae576eada5c) utility.cc (5141:a3b0e3a8b83c)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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70 panic("getArgument() only implemented for FULL_SYSTEM\n");
71 M5_DUMMY_RETURN
72#endif
73}
74
75# if FULL_SYSTEM
76void initCPU(ThreadContext *tc, int cpuId)
77{
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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70 panic("getArgument() only implemented for FULL_SYSTEM\n");
71 M5_DUMMY_RETURN
72#endif
73}
74
75# if FULL_SYSTEM
76void initCPU(ThreadContext *tc, int cpuId)
77{
78 // TODO Figure out what the attribute registers should be set to. How this
79 // information is stored isn't specified, but it's values are in table
80 // 14.2.
81
82 // The otherwise unmodified integer registers should be set to 0.
83 for (int index = 0; index < NUM_INTREGS; index++) {
84 tc->setIntReg(index, 0);
85 }
86
87 // These next two loops zero internal microcode and implicit registers.
88 // They aren't specified by the ISA but are used internally by M5's
89 // implementation.

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106 tc->setMiscReg(MISCREG_CR3, 0);
107 tc->setMiscReg(MISCREG_CR4, 0);
108 tc->setMiscReg(MISCREG_CR8, 0);
109
110 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
111
112 tc->setMiscReg(MISCREG_EFER, 0);
113
78 // The otherwise unmodified integer registers should be set to 0.
79 for (int index = 0; index < NUM_INTREGS; index++) {
80 tc->setIntReg(index, 0);
81 }
82
83 // These next two loops zero internal microcode and implicit registers.
84 // They aren't specified by the ISA but are used internally by M5's
85 // implementation.

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102 tc->setMiscReg(MISCREG_CR3, 0);
103 tc->setMiscReg(MISCREG_CR4, 0);
104 tc->setMiscReg(MISCREG_CR8, 0);
105
106 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
107
108 tc->setMiscReg(MISCREG_EFER, 0);
109
110 SegAttr dataAttr = 0;
111 dataAttr.writable = 1;
112 dataAttr.readable = 1;
113 dataAttr.expandDown = 0;
114 dataAttr.dpl = 0;
115 dataAttr.defaultSize = 0;
116
114 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
115 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
116 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
117 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
117 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
118 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
119 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
120 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
118 tc->setMiscReg(MISCREG_SEG_ATTR(seg), 0);
121 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
119 }
120
122 }
123
124 SegAttr codeAttr = 0;
125 codeAttr.writable = 0;
126 codeAttr.readable = 1;
127 codeAttr.expandDown = 0;
128 codeAttr.dpl = 0;
129 codeAttr.defaultSize = 0;
130
121 tc->setMiscReg(MISCREG_CS, 0xf000);
122 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
123 // This has the base value pre-added.
124 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
131 tc->setMiscReg(MISCREG_CS, 0xf000);
132 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
133 // This has the base value pre-added.
134 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
125 tc->setMiscReg(MISCREG_CS_ATTR, 0);
135 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
126
127 tc->setPC(0x000000000000fff0 +
128 tc->readMiscReg(MISCREG_CS_BASE));
129 tc->setNextPC(tc->readPC() + sizeof(MachInst));
130
131 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
132 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
133

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146
147 // This value should be the family/model/stepping of the processor.
148 // (page 418). It should be consistent with the value from CPUID, but the
149 // actual value probably doesn't matter much.
150 tc->setIntReg(INTREG_RDX, 0);
151
152 // TODO initialize x87, 64 bit, and 128 bit media state
153
136
137 tc->setPC(0x000000000000fff0 +
138 tc->readMiscReg(MISCREG_CS_BASE));
139 tc->setNextPC(tc->readPC() + sizeof(MachInst));
140
141 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
142 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
143

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156
157 // This value should be the family/model/stepping of the processor.
158 // (page 418). It should be consistent with the value from CPUID, but the
159 // actual value probably doesn't matter much.
160 tc->setIntReg(INTREG_RDX, 0);
161
162 // TODO initialize x87, 64 bit, and 128 bit media state
163
154 // TODO Set up MTRRs (page 512)
164 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
165 for (int i = 0; i < 8; i++) {
166 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
167 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
168 }
169 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
170 tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
171 tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
172 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
173 tc->setMiscReg(MISCREG_MTRR_FIX_4k_C8000, 0);
174 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
175 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
176 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
177 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
178 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
179 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
155
180
156 // TODO Set up machine check registers (page 515)
181 tc->setMiscReg(MISCREG_DEF_TYPE, 0);
157
182
183 tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
184 tc->setMiscReg(MISCREG_MCG_STATUS, 0);
185 tc->setMiscReg(MISCREG_MCG_CTL, 0);
186
187 for (int i = 0; i < 5; i++) {
188 tc->setMiscReg(MISCREG_MC_CTL(i), 0);
189 tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
190 tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
191 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
192 }
193
158 tc->setMiscReg(MISCREG_DR0, 0);
159 tc->setMiscReg(MISCREG_DR1, 0);
160 tc->setMiscReg(MISCREG_DR2, 0);
161 tc->setMiscReg(MISCREG_DR3, 0);
162
163 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
164 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
165
194 tc->setMiscReg(MISCREG_DR0, 0);
195 tc->setMiscReg(MISCREG_DR1, 0);
196 tc->setMiscReg(MISCREG_DR2, 0);
197 tc->setMiscReg(MISCREG_DR3, 0);
198
199 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
200 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
201
166 // TODO Set time stamp counter to 0
202 tc->setMiscReg(MISCREG_TSC, 0);
203 tc->setMiscReg(MISCREG_TSC_AUX, 0);
167
204
168 // TODO Set up performance monitoring registers (page 517)
205 for (int i = 0; i < 4; i++) {
206 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
207 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
208 }
169
209
170 // TODO Set up the rest of the MSRs (page 507)
210 tc->setMiscReg(MISCREG_STAR, 0);
211 tc->setMiscReg(MISCREG_LSTAR, 0);
212 tc->setMiscReg(MISCREG_CSTAR, 0);
171
213
214 tc->setMiscReg(MISCREG_SF_MASK, 0);
215
216 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
217
218 tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
219 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
220 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
221
222 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406);
223
224 tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
225
226 tc->setMiscReg(MISCREG_IORR_BASE0, 0);
227 tc->setMiscReg(MISCREG_IORR_BASE1, 0);
228
229 tc->setMiscReg(MISCREG_IORR_MASK0, 0);
230 tc->setMiscReg(MISCREG_IORR_MASK1, 0);
231
232 tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
233 tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
234
235 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
236 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
237 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
238 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
239 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
240
172 // Invalidate the caches (this should already be done for us)
173
174 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
175 // currently being handled at all.
176
241 // Invalidate the caches (this should already be done for us)
242
243 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
244 // currently being handled at all.
245
177 // Set the SMRAM base address (SMBASE) to 0x00030000
246 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
247
248 tc->setMiscReg(MISCREG_VM_CR, 0);
249 tc->setMiscReg(MISCREG_IGNNE, 0);
250 tc->setMiscReg(MISCREG_SMM_CTL, 0);
251 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
178}
179
180#endif
181
182void startupCPU(ThreadContext *tc, int cpuId)
183{
184 if (cpuId == 0) {
185 // This is the boot strap processor (BSP). Initialize it to look like

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253
254#endif
255
256void startupCPU(ThreadContext *tc, int cpuId)
257{
258 if (cpuId == 0) {
259 // This is the boot strap processor (BSP). Initialize it to look like

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