1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "config/full_system.hh"
41
42#if FULL_SYSTEM
43#include "arch/x86/interrupts.hh"
44#endif
45#include "arch/x86/regs/int.hh"
46#include "arch/x86/regs/misc.hh"
47#include "arch/x86/regs/segment.hh"
48#include "arch/x86/utility.hh"
49#include "arch/x86/x86_traits.hh"
50#include "cpu/base.hh"
51#include "sim/system.hh"
52
53namespace X86ISA {
54
| 1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include "config/full_system.hh"
41
42#if FULL_SYSTEM
43#include "arch/x86/interrupts.hh"
44#endif
45#include "arch/x86/regs/int.hh"
46#include "arch/x86/regs/misc.hh"
47#include "arch/x86/regs/segment.hh"
48#include "arch/x86/utility.hh"
49#include "arch/x86/x86_traits.hh"
50#include "cpu/base.hh"
51#include "sim/system.hh"
52
53namespace X86ISA {
54
|
56#if FULL_SYSTEM
57 panic("getArgument() not implemented for x86!\n");
58#else
59 panic("getArgument() only implemented for FULL_SYSTEM\n");
60 M5_DUMMY_RETURN
61#endif
62}
63
64# if FULL_SYSTEM
65void initCPU(ThreadContext *tc, int cpuId)
66{
67 // This function is essentially performing a reset. The actual INIT
68 // interrupt does a subset of this, so we'll piggyback on some of its
69 // functionality.
70 InitInterrupt init(0);
71 init.invoke(tc);
72
73 tc->setMicroPC(0);
74 tc->setNextMicroPC(1);
75
76 // These next two loops zero internal microcode and implicit registers.
77 // They aren't specified by the ISA but are used internally by M5's
78 // implementation.
79 for (int index = 0; index < NumMicroIntRegs; index++) {
80 tc->setIntReg(INTREG_MICRO(index), 0);
81 }
82
83 for (int index = 0; index < NumImplicitIntRegs; index++) {
84 tc->setIntReg(INTREG_IMPLICIT(index), 0);
85 }
86
87 // Set integer register EAX to 0 to indicate that the optional BIST
88 // passed. No BIST actually runs, but software may still check this
89 // register for errors.
90 tc->setIntReg(INTREG_RAX, 0);
91
92 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
93 tc->setMiscReg(MISCREG_CR8, 0);
94
95 // TODO initialize x87, 64 bit, and 128 bit media state
96
97 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
98 for (int i = 0; i < 8; i++) {
99 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
100 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
101 }
102 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
103 tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
104 tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
105 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
106 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
107 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
108 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
109 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
110 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
111 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
112 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
113
114 tc->setMiscReg(MISCREG_DEF_TYPE, 0);
115
116 tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
117 tc->setMiscReg(MISCREG_MCG_STATUS, 0);
118 tc->setMiscReg(MISCREG_MCG_CTL, 0);
119
120 for (int i = 0; i < 5; i++) {
121 tc->setMiscReg(MISCREG_MC_CTL(i), 0);
122 tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
123 tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
124 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
125 }
126
127 tc->setMiscReg(MISCREG_TSC, 0);
128 tc->setMiscReg(MISCREG_TSC_AUX, 0);
129
130 for (int i = 0; i < 4; i++) {
131 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
132 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
133 }
134
135 tc->setMiscReg(MISCREG_STAR, 0);
136 tc->setMiscReg(MISCREG_LSTAR, 0);
137 tc->setMiscReg(MISCREG_CSTAR, 0);
138
139 tc->setMiscReg(MISCREG_SF_MASK, 0);
140
141 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
142
143 tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
144 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
145 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
146
147 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
148
149 tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
150
151 tc->setMiscReg(MISCREG_IORR_BASE0, 0);
152 tc->setMiscReg(MISCREG_IORR_BASE1, 0);
153
154 tc->setMiscReg(MISCREG_IORR_MASK0, 0);
155 tc->setMiscReg(MISCREG_IORR_MASK1, 0);
156
157 tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
158 tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
159
160 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
161 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
162 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
163 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
164 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
165
166 // Invalidate the caches (this should already be done for us)
167
168 LocalApicBase lApicBase = 0;
169 lApicBase.base = 0xFEE00000 >> 12;
170 lApicBase.enable = 1;
171 lApicBase.bsp = (cpuId == 0);
172 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
173
174 Interrupts * interrupts = dynamic_cast<Interrupts *>(
175 tc->getCpuPtr()->getInterruptController());
176 assert(interrupts);
177
178 interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
179
180 interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
181
182 interrupts->setClock(tc->getCpuPtr()->ticks(16));
183
184 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
185
186 tc->setMiscReg(MISCREG_VM_CR, 0);
187 tc->setMiscReg(MISCREG_IGNNE, 0);
188 tc->setMiscReg(MISCREG_SMM_CTL, 0);
189 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
190}
191
192#endif
193
194void startupCPU(ThreadContext *tc, int cpuId)
195{
196#if FULL_SYSTEM
197 if (cpuId == 0) {
198 tc->activate(0);
199 } else {
200 // This is an application processor (AP). It should be initialized to
201 // look like only the BIOS POST has run on it and put then put it into
202 // a halted state.
203 tc->suspend(0);
204 }
205#else
206 tc->activate(0);
207#endif
208}
209
210void
211copyMiscRegs(ThreadContext *src, ThreadContext *dest)
212{
213 warn("copyMiscRegs is naively implemented for x86\n");
214 for (int i = 0; i < NUM_MISCREGS; ++i) {
215 if ( ( i != MISCREG_CR1 &&
216 !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
217 !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
218 continue;
219 }
220 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
221 }
222}
223
224void
225copyRegs(ThreadContext *src, ThreadContext *dest)
226{
227 panic("copyRegs not implemented for x86!\n");
228 //copy int regs
229 //copy float regs
230 copyMiscRegs(src, dest);
231
232 dest->setPC(src->readPC());
233 dest->setNextPC(src->readNextPC());
234}
235
236void
237skipFunction(ThreadContext *tc)
238{
239 panic("Not implemented for x86\n");
240}
241
242
243} //namespace X86_ISA
| 58#if FULL_SYSTEM
59 panic("getArgument() not implemented for x86!\n");
60#else
61 panic("getArgument() only implemented for FULL_SYSTEM\n");
62 M5_DUMMY_RETURN
63#endif
64}
65
66# if FULL_SYSTEM
67void initCPU(ThreadContext *tc, int cpuId)
68{
69 // This function is essentially performing a reset. The actual INIT
70 // interrupt does a subset of this, so we'll piggyback on some of its
71 // functionality.
72 InitInterrupt init(0);
73 init.invoke(tc);
74
75 tc->setMicroPC(0);
76 tc->setNextMicroPC(1);
77
78 // These next two loops zero internal microcode and implicit registers.
79 // They aren't specified by the ISA but are used internally by M5's
80 // implementation.
81 for (int index = 0; index < NumMicroIntRegs; index++) {
82 tc->setIntReg(INTREG_MICRO(index), 0);
83 }
84
85 for (int index = 0; index < NumImplicitIntRegs; index++) {
86 tc->setIntReg(INTREG_IMPLICIT(index), 0);
87 }
88
89 // Set integer register EAX to 0 to indicate that the optional BIST
90 // passed. No BIST actually runs, but software may still check this
91 // register for errors.
92 tc->setIntReg(INTREG_RAX, 0);
93
94 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010ULL);
95 tc->setMiscReg(MISCREG_CR8, 0);
96
97 // TODO initialize x87, 64 bit, and 128 bit media state
98
99 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
100 for (int i = 0; i < 8; i++) {
101 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
102 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
103 }
104 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
105 tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
106 tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
107 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
108 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
109 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
110 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
111 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
112 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
113 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
114 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
115
116 tc->setMiscReg(MISCREG_DEF_TYPE, 0);
117
118 tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
119 tc->setMiscReg(MISCREG_MCG_STATUS, 0);
120 tc->setMiscReg(MISCREG_MCG_CTL, 0);
121
122 for (int i = 0; i < 5; i++) {
123 tc->setMiscReg(MISCREG_MC_CTL(i), 0);
124 tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
125 tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
126 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
127 }
128
129 tc->setMiscReg(MISCREG_TSC, 0);
130 tc->setMiscReg(MISCREG_TSC_AUX, 0);
131
132 for (int i = 0; i < 4; i++) {
133 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
134 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
135 }
136
137 tc->setMiscReg(MISCREG_STAR, 0);
138 tc->setMiscReg(MISCREG_LSTAR, 0);
139 tc->setMiscReg(MISCREG_CSTAR, 0);
140
141 tc->setMiscReg(MISCREG_SF_MASK, 0);
142
143 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
144
145 tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
146 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
147 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
148
149 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406ULL);
150
151 tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
152
153 tc->setMiscReg(MISCREG_IORR_BASE0, 0);
154 tc->setMiscReg(MISCREG_IORR_BASE1, 0);
155
156 tc->setMiscReg(MISCREG_IORR_MASK0, 0);
157 tc->setMiscReg(MISCREG_IORR_MASK1, 0);
158
159 tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
160 tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
161
162 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
163 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
164 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
165 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
166 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
167
168 // Invalidate the caches (this should already be done for us)
169
170 LocalApicBase lApicBase = 0;
171 lApicBase.base = 0xFEE00000 >> 12;
172 lApicBase.enable = 1;
173 lApicBase.bsp = (cpuId == 0);
174 tc->setMiscReg(MISCREG_APIC_BASE, lApicBase);
175
176 Interrupts * interrupts = dynamic_cast<Interrupts *>(
177 tc->getCpuPtr()->getInterruptController());
178 assert(interrupts);
179
180 interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
181
182 interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
183
184 interrupts->setClock(tc->getCpuPtr()->ticks(16));
185
186 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
187
188 tc->setMiscReg(MISCREG_VM_CR, 0);
189 tc->setMiscReg(MISCREG_IGNNE, 0);
190 tc->setMiscReg(MISCREG_SMM_CTL, 0);
191 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
192}
193
194#endif
195
196void startupCPU(ThreadContext *tc, int cpuId)
197{
198#if FULL_SYSTEM
199 if (cpuId == 0) {
200 tc->activate(0);
201 } else {
202 // This is an application processor (AP). It should be initialized to
203 // look like only the BIOS POST has run on it and put then put it into
204 // a halted state.
205 tc->suspend(0);
206 }
207#else
208 tc->activate(0);
209#endif
210}
211
212void
213copyMiscRegs(ThreadContext *src, ThreadContext *dest)
214{
215 warn("copyMiscRegs is naively implemented for x86\n");
216 for (int i = 0; i < NUM_MISCREGS; ++i) {
217 if ( ( i != MISCREG_CR1 &&
218 !(i > MISCREG_CR4 && i < MISCREG_CR8) &&
219 !(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
220 continue;
221 }
222 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
223 }
224}
225
226void
227copyRegs(ThreadContext *src, ThreadContext *dest)
228{
229 panic("copyRegs not implemented for x86!\n");
230 //copy int regs
231 //copy float regs
232 copyMiscRegs(src, dest);
233
234 dest->setPC(src->readPC());
235 dest->setNextPC(src->readNextPC());
236}
237
238void
239skipFunction(ThreadContext *tc)
240{
241 panic("Not implemented for x86\n");
242}
243
244
245} //namespace X86_ISA
|