1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
30 * other materials provided with the distribution. Neither the name of
31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/intregs.hh"
59#include "arch/x86/miscregs.hh"
60#include "arch/x86/segmentregs.hh"
61#include "arch/x86/utility.hh"
62#include "arch/x86/x86_traits.hh"
63#include "sim/system.hh"
64
65namespace X86ISA {
66
67uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
68#if FULL_SYSTEM
69 panic("getArgument() not implemented for x86!\n");
70#else
71 panic("getArgument() only implemented for FULL_SYSTEM\n");
72 M5_DUMMY_RETURN
73#endif
74}
75
76# if FULL_SYSTEM
77void initCPU(ThreadContext *tc, int cpuId)
78{
79 // The otherwise unmodified integer registers should be set to 0.
80 for (int index = 0; index < NUM_INTREGS; index++) {
81 tc->setIntReg(index, 0);
82 }
83
84 // These next two loops zero internal microcode and implicit registers.
85 // They aren't specified by the ISA but are used internally by M5's
86 // implementation.
87 for (int index = 0; index < NumMicroIntRegs; index++) {
88 tc->setIntReg(INTREG_MICRO(index), 0);
89 }
90
91 for (int index = 0; index < NumImplicitIntRegs; index++) {
92 tc->setIntReg(INTREG_IMPLICIT(index), 0);
93 }
94
95 // Set integer register EAX to 0 to indicate that the optional BIST
96 // passed. No BIST actually runs, but software may still check this
97 // register for errors.
98 tc->setIntReg(INTREG_RAX, 0);
99
100 //The following values are dictated by the architecture for after a RESET#
101 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010);
102 tc->setMiscReg(MISCREG_CR2, 0);
103 tc->setMiscReg(MISCREG_CR3, 0);
104 tc->setMiscReg(MISCREG_CR4, 0);
105 tc->setMiscReg(MISCREG_CR8, 0);
106
107 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
108
109 tc->setMiscReg(MISCREG_EFER, 0);
110
111 SegAttr dataAttr = 0;
112 dataAttr.writable = 1;
113 dataAttr.readable = 1;
114 dataAttr.expandDown = 0;
115 dataAttr.dpl = 0;
116 dataAttr.defaultSize = 0;
117
118 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
119 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
120 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
121 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
122 tc->setMiscReg(MISCREG_SEG_ATTR(seg), dataAttr);
123 }
124
125 SegAttr codeAttr = 0;
126 codeAttr.writable = 0;
127 codeAttr.readable = 1;
128 codeAttr.expandDown = 0;
129 codeAttr.dpl = 0;
130 codeAttr.defaultSize = 0;
131
132 tc->setMiscReg(MISCREG_CS, 0xf000);
133 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
134 // This has the base value pre-added.
135 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
136 tc->setMiscReg(MISCREG_CS_ATTR, codeAttr);
137
138 tc->setPC(0x000000000000fff0 +
139 tc->readMiscReg(MISCREG_CS_BASE));
140 tc->setNextPC(tc->readPC() + sizeof(MachInst));
141
142 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
143 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
144
145 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
146 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
147
148 tc->setMiscReg(MISCREG_LDTR, 0);
149 tc->setMiscReg(MISCREG_LDTR_BASE, 0);
150 tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff);
151 tc->setMiscReg(MISCREG_LDTR_ATTR, 0);
152
153 tc->setMiscReg(MISCREG_TR, 0);
154 tc->setMiscReg(MISCREG_TR_BASE, 0);
155 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
156 tc->setMiscReg(MISCREG_TR_ATTR, 0);
157
158 // This value should be the family/model/stepping of the processor.
159 // (page 418). It should be consistent with the value from CPUID, but the
160 // actual value probably doesn't matter much.
161 tc->setIntReg(INTREG_RDX, 0);
162
163 // TODO initialize x87, 64 bit, and 128 bit media state
164
165 tc->setMiscReg(MISCREG_MTRRCAP, 0x0508);
166 for (int i = 0; i < 8; i++) {
167 tc->setMiscReg(MISCREG_MTRR_PHYS_BASE(i), 0);
168 tc->setMiscReg(MISCREG_MTRR_PHYS_MASK(i), 0);
169 }
170 tc->setMiscReg(MISCREG_MTRR_FIX_64K_00000, 0);
171 tc->setMiscReg(MISCREG_MTRR_FIX_16K_80000, 0);
172 tc->setMiscReg(MISCREG_MTRR_FIX_16K_A0000, 0);
173 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C0000, 0);
174 tc->setMiscReg(MISCREG_MTRR_FIX_4K_C8000, 0);
175 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D0000, 0);
176 tc->setMiscReg(MISCREG_MTRR_FIX_4K_D8000, 0);
177 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E0000, 0);
178 tc->setMiscReg(MISCREG_MTRR_FIX_4K_E8000, 0);
179 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F0000, 0);
180 tc->setMiscReg(MISCREG_MTRR_FIX_4K_F8000, 0);
181
182 tc->setMiscReg(MISCREG_DEF_TYPE, 0);
183
184 tc->setMiscReg(MISCREG_MCG_CAP, 0x104);
185 tc->setMiscReg(MISCREG_MCG_STATUS, 0);
186 tc->setMiscReg(MISCREG_MCG_CTL, 0);
187
188 for (int i = 0; i < 5; i++) {
189 tc->setMiscReg(MISCREG_MC_CTL(i), 0);
190 tc->setMiscReg(MISCREG_MC_STATUS(i), 0);
191 tc->setMiscReg(MISCREG_MC_ADDR(i), 0);
192 tc->setMiscReg(MISCREG_MC_MISC(i), 0);
193 }
194
195 tc->setMiscReg(MISCREG_DR0, 0);
196 tc->setMiscReg(MISCREG_DR1, 0);
197 tc->setMiscReg(MISCREG_DR2, 0);
198 tc->setMiscReg(MISCREG_DR3, 0);
199
200 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
201 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
202
203 tc->setMiscReg(MISCREG_TSC, 0);
204 tc->setMiscReg(MISCREG_TSC_AUX, 0);
205
206 for (int i = 0; i < 4; i++) {
207 tc->setMiscReg(MISCREG_PERF_EVT_SEL(i), 0);
208 tc->setMiscReg(MISCREG_PERF_EVT_CTR(i), 0);
209 }
210
211 tc->setMiscReg(MISCREG_STAR, 0);
212 tc->setMiscReg(MISCREG_LSTAR, 0);
213 tc->setMiscReg(MISCREG_CSTAR, 0);
214
215 tc->setMiscReg(MISCREG_SF_MASK, 0);
216
217 tc->setMiscReg(MISCREG_KERNEL_GS_BASE, 0);
218
219 tc->setMiscReg(MISCREG_SYSENTER_CS, 0);
220 tc->setMiscReg(MISCREG_SYSENTER_ESP, 0);
221 tc->setMiscReg(MISCREG_SYSENTER_EIP, 0);
222
223 tc->setMiscReg(MISCREG_PAT, 0x0007040600070406);
224
225 tc->setMiscReg(MISCREG_SYSCFG, 0x20601);
226
227 tc->setMiscReg(MISCREG_IORR_BASE0, 0);
228 tc->setMiscReg(MISCREG_IORR_BASE1, 0);
229
230 tc->setMiscReg(MISCREG_IORR_MASK0, 0);
231 tc->setMiscReg(MISCREG_IORR_MASK1, 0);
232
233 tc->setMiscReg(MISCREG_TOP_MEM, 0x4000000);
234 tc->setMiscReg(MISCREG_TOP_MEM2, 0x0);
235
236 tc->setMiscReg(MISCREG_DEBUG_CTL_MSR, 0);
237 tc->setMiscReg(MISCREG_LAST_BRANCH_FROM_IP, 0);
238 tc->setMiscReg(MISCREG_LAST_BRANCH_TO_IP, 0);
239 tc->setMiscReg(MISCREG_LAST_EXCEPTION_FROM_IP, 0);
240 tc->setMiscReg(MISCREG_LAST_EXCEPTION_TO_IP, 0);
241
242 // Invalidate the caches (this should already be done for us)
243
244 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
245 // currently being handled at all.
246
247 // TODO Set the SMRAM base address (SMBASE) to 0x00030000
248
249 tc->setMiscReg(MISCREG_VM_CR, 0);
250 tc->setMiscReg(MISCREG_IGNNE, 0);
251 tc->setMiscReg(MISCREG_SMM_CTL, 0);
252 tc->setMiscReg(MISCREG_VM_HSAVE_PA, 0);
253}
254
255#endif
256
257#if FULL_SYSTEM
258void startupCPU(ThreadContext *tc, int cpuId)
259{
260 if (cpuId == 0) {
261 // This is the boot strap processor (BSP). Initialize it to look like
262 // the boot loader has just turned control over to the 64 bit OS. We
263 // won't actually set up real mode or legacy protected mode descriptor
264 // tables because we aren't executing any code that would require
265 // them. We do, however toggle the control bits in the correct order
266 // while allowing consistency checks and the underlying mechansims
267 // just to be safe.
268
269 const int NumPDTs = 4;
270
271 const Addr PageMapLevel4 = 0x70000;
272 const Addr PageDirPtrTable = 0x71000;
273 const Addr PageDirTable[NumPDTs] =
274 {0x72000, 0x73000, 0x74000, 0x75000};
275 const Addr GDTBase = 0x76000;
276
277 const int PML4Bits = 9;
278 const int PDPTBits = 9;
279 const int PDTBits = 9;
280
281 // Get a port to write the page tables and descriptor tables.
282 FunctionalPort * physPort = tc->getPhysPort();
283
284 /*
285 * Set up the gdt.
286 */
287 // Place holder at selector 0
288 uint64_t nullDescriptor = 0;
289 physPort->writeBlob(GDTBase, (uint8_t *)(&nullDescriptor), 8);
290
291 //64 bit code segment
292 SegDescriptor csDesc = 0;
293 csDesc.type.c = 0; // Not conforming
294 csDesc.dpl = 0; // Privelege level 0
295 csDesc.p = 1; // Present
296 csDesc.l = 1; // 64 bit
297 csDesc.d = 0; // default operand size
298 //Because we're dealing with a pointer and I don't think it's
299 //guaranteed that there isn't anything in a nonvirtual class between
300 //it's beginning in memory and it's actual data, we'll use an
301 //intermediary.
302 uint64_t csDescVal = csDesc;
303 physPort->writeBlob(GDTBase, (uint8_t *)(&csDescVal), 8);
304
305 tc->setMiscReg(MISCREG_GDTR_BASE, GDTBase);
306 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xF);
307
308 /*
309 * Identity map the first 4GB of memory. In order to map this region
310 * of memory in long mode, there needs to be one actual page map level
311 * 4 entry which points to one page directory pointer table which
312 * points to 4 different page directory tables which are full of two
313 * megabyte pages. All of the other entries in valid tables are set
314 * to indicate that they don't pertain to anything valid and will
315 * cause a fault if used.
316 */
317
318 // Put valid values in all of the various table entries which indicate
319 // that those entries don't point to further tables or pages. Then
320 // set the values of those entries which are needed.
321
322 // Page Map Level 4
323
324 // read/write, user, not present
325 uint64_t pml4e = X86ISA::htog(0x6);
326 for (int offset = 0; offset < (1 << PML4Bits) * 8; offset += 8) {
327 physPort->writeBlob(PageMapLevel4 + offset, (uint8_t *)(&pml4e), 8);
328 }
329 // Point to the only PDPT
330 pml4e = X86ISA::htog(0x7 | PageDirPtrTable);
331 physPort->writeBlob(PageMapLevel4, (uint8_t *)(&pml4e), 8);
332
333 // Page Directory Pointer Table
334
335 // read/write, user, not present
336 uint64_t pdpe = X86ISA::htog(0x6);
337 for (int offset = 0; offset < (1 << PDPTBits) * 8; offset += 8) {
338 physPort->writeBlob(PageDirPtrTable + offset,
339 (uint8_t *)(&pdpe), 8);
340 }
341 // Point to the PDTs
342 for (int table = 0; table < NumPDTs; table++) {
343 pdpe = X86ISA::htog(0x7 | PageDirTable[table]);
344 physPort->writeBlob(PageDirPtrTable + table * 8,
345 (uint8_t *)(&pdpe), 8);
346 }
347
348 // Page Directory Tables
349
350 Addr base = 0;
351 const Addr pageSize = 2 << 20;
352 for (int table = 0; table < NumPDTs; table++) {
353 for (int offset = 0; offset < (1 << PDTBits) * 8; offset += 8) {
354 // read/write, user, present, 4MB
355 uint64_t pdte = X86ISA::htog(0x87 | base);
356 physPort->writeBlob(PageDirTable[table] + offset,
357 (uint8_t *)(&pdte), 8);
358 base += pageSize;
359 }
360 }
361
362 /*
363 * Transition from real mode all the way up to Long mode
364 */
365 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
366 //Turn off paging.
367 cr0.pg = 0;
368 tc->setMiscReg(MISCREG_CR0, cr0);
369 //Turn on protected mode.
370 cr0.pe = 1;
371 tc->setMiscReg(MISCREG_CR0, cr0);
372
373 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
374 //Turn on pae.
375 cr4.pae = 1;
376 tc->setMiscReg(MISCREG_CR4, cr4);
377
378 //Point to the page tables.
379 tc->setMiscReg(MISCREG_CR3, PageMapLevel4);
380
381 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
382 //Enable long mode.
383 efer.lme = 1;
384 tc->setMiscReg(MISCREG_EFER, efer);
385
386 //Activate long mode.
387 cr0.pg = 1;
388 tc->setMiscReg(MISCREG_CR0, cr0);
389
390 /*
391 * Far jump into 64 bit mode.
392 */
393 // Set the selector
394 tc->setMiscReg(MISCREG_CS, 1);
395 // Manually set up the segment attributes. In the future when there's
396 // other existing functionality to do this, that could be used
397 // instead.
398 SegAttr csAttr = 0;
399 csAttr.writable = 0;
400 csAttr.readable = 1;
401 csAttr.expandDown = 0;
402 csAttr.dpl = 0;
403 csAttr.defaultSize = 0;
404 csAttr.longMode = 1;
405 tc->setMiscReg(MISCREG_CS_ATTR, csAttr);
406
407 tc->setPC(tc->getSystemPtr()->kernelEntry);
408 tc->setNextPC(tc->readPC());
409
410 // We should now be in long mode. Yay!
411
412 tc->activate(0);
413 } else {
414 // This is an application processor (AP). It should be initialized to
415 // look like only the BIOS POST has run on it and put then put it into
416 // a halted state.
417 tc->suspend();
418 }
419}
420
421#else
422
423void startupCPU(ThreadContext *tc, int cpuId)
424{
425 tc->activate(0);
426}
427
428#endif
429
430} //namespace X86_ISA