1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *
9 * The software must be used only for Non-Commercial Use which means any
10 * use which is NOT directed to receiving any direct monetary
11 * compensation for, or commercial advantage from such use. Illustrative
12 * examples of non-commercial use are academic research, personal study,
13 * teaching, education and corporate research & development.
14 * Illustrative examples of commercial use are distributing products for
15 * commercial advantage and providing services using the software for
16 * commercial advantage.
17 *
18 * If you wish to use this software or functionality therein that may be
19 * covered by patents for commercial use, please contact:
20 * Director of Intellectual Property Licensing
21 * Office of Strategy and Technology
22 * Hewlett-Packard Company
23 * 1501 Page Mill Road
24 * Palo Alto, California 94304
25 *
26 * Redistributions of source code must retain the above copyright notice,
27 * this list of conditions and the following disclaimer. Redistributions
28 * in binary form must reproduce the above copyright notice, this list of
29 * conditions and the following disclaimer in the documentation and/or
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31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
32 * contributors may be used to endorse or promote products derived from
33 * this software without specific prior written permission. No right of
34 * sublicense is granted herewith. Derivatives of the software and
35 * output created using the software may be prepared, but only for
36 * Non-Commercial Uses. Derivatives of the software may be shared with
37 * others provided: (i) the others agree to abide by the list of
38 * conditions herein which includes the Non-Commercial Use restrictions;
39 * and (ii) such Derivatives of the software include the above copyright
40 * notice to acknowledge the contribution from this software where
41 * applicable, this list of conditions and the disclaimer below.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * Authors: Gabe Black
56 */
57
58#include "arch/x86/intregs.hh"
59#include "arch/x86/miscregs.hh"
60#include "arch/x86/segmentregs.hh"
61#include "arch/x86/utility.hh"
62#include "arch/x86/x86_traits.hh"
63
64namespace X86ISA {
65
66uint64_t getArgument(ThreadContext *tc, int number, bool fp) {
67#if FULL_SYSTEM
68 panic("getArgument() not implemented for x86!\n");
69#else
70 panic("getArgument() only implemented for FULL_SYSTEM\n");
71 M5_DUMMY_RETURN
72#endif
73}
74
75# if FULL_SYSTEM
76void initCPU(ThreadContext *tc, int cpuId)
77{
78 // TODO Figure out what the attribute registers should be set to. How this
79 // information is stored isn't specified, but it's values are in table
80 // 14.2.
81
82 // The otherwise unmodified integer registers should be set to 0.
83 for (int index = 0; index < NUM_INTREGS; index++) {
84 tc->setIntReg(index, 0);
85 }
86
87 // These next two loops zero internal microcode and implicit registers.
88 // They aren't specified by the ISA but are used internally by M5's
89 // implementation.
90 for (int index = 0; index < NumMicroIntRegs; index++) {
91 tc->setIntReg(INTREG_MICRO(index), 0);
92 }
93
94 for (int index = 0; index < NumImplicitIntRegs; index++) {
95 tc->setIntReg(INTREG_IMPLICIT(index), 0);
96 }
97
98 // Set integer register EAX to 0 to indicate that the optional BIST
99 // passed. No BIST actually runs, but software may still check this
100 // register for errors.
101 tc->setIntReg(INTREG_RAX, 0);
102
103 //The following values are dictated by the architecture for after a RESET#
104 tc->setMiscReg(MISCREG_CR0, 0x0000000060000010);
105 tc->setMiscReg(MISCREG_CR2, 0);
106 tc->setMiscReg(MISCREG_CR3, 0);
107 tc->setMiscReg(MISCREG_CR4, 0);
108 tc->setMiscReg(MISCREG_CR8, 0);
109
110 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
111
112 tc->setMiscReg(MISCREG_EFER, 0);
113
114 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
115 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
116 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
117 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
118 tc->setMiscReg(MISCREG_SEG_ATTR(seg), 0);
119 }
120
121 tc->setMiscReg(MISCREG_CS, 0xf000);
122 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
123 // This has the base value pre-added.
124 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
125 tc->setMiscReg(MISCREG_CS_ATTR, 0);
126
127 tc->setPC(0x000000000000fff0 +
128 tc->readMiscReg(MISCREG_CS_BASE));
129 tc->setNextPC(tc->readPC() + sizeof(MachInst));
130
131 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
132 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
133
134 tc->setMiscReg(MISCREG_IDTR_BASE, 0);
135 tc->setMiscReg(MISCREG_IDTR_LIMIT, 0xffff);
136
137 tc->setMiscReg(MISCREG_LDTR, 0);
138 tc->setMiscReg(MISCREG_LDTR_BASE, 0);
139 tc->setMiscReg(MISCREG_LDTR_LIMIT, 0xffff);
140 tc->setMiscReg(MISCREG_LDTR_ATTR, 0);
141
142 tc->setMiscReg(MISCREG_TR, 0);
143 tc->setMiscReg(MISCREG_TR_BASE, 0);
144 tc->setMiscReg(MISCREG_TR_LIMIT, 0xffff);
145 tc->setMiscReg(MISCREG_TR_ATTR, 0);
146
147 // This value should be the family/model/stepping of the processor.
148 // (page 418). It should be consistent with the value from CPUID, but the
149 // actual value probably doesn't matter much.
150 tc->setIntReg(INTREG_RDX, 0);
151
152 // TODO initialize x87, 64 bit, and 128 bit media state
153
154 // TODO Set up MTRRs (page 512)
155
156 // TODO Set up machine check registers (page 515)
157
158 tc->setMiscReg(MISCREG_DR0, 0);
159 tc->setMiscReg(MISCREG_DR1, 0);
160 tc->setMiscReg(MISCREG_DR2, 0);
161 tc->setMiscReg(MISCREG_DR3, 0);
162
163 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
164 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
165
166 // TODO Set time stamp counter to 0
167
168 // TODO Set up performance monitoring registers (page 517)
169
170 // TODO Set up the rest of the MSRs (page 507)
171
172 // Invalidate the caches (this should already be done for us)
173
174 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
175 // currently being handled at all.
176
177 // Set the SMRAM base address (SMBASE) to 0x00030000
178}
179
180#endif
181
182void startupCPU(ThreadContext *tc, int cpuId)
183{
184 if (cpuId == 0) {
185 // This is the boot strap processor (BSP). Initialize it to look like
186 // the boot loader has just turned control over to the 64 bit OS.
187
188 // Enable paging, turn on long mode, etc.
189
190 tc->activate(0);
191 } else {
192 // This is an application processor (AP). It should be initialized to
193 // look like only the BIOS POST has run on it and put then put it into
194 // a halted state.
195 }
196}
197
198} //namespace X86_ISA