1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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70 panic("getArgument() only implemented for FULL_SYSTEM\n");
71 M5_DUMMY_RETURN
72#endif
73}
74
75# if FULL_SYSTEM
76void initCPU(ThreadContext *tc, int cpuId)
77{
78 // TODO Figure out what the attribute registers should be set to. How this
79 // information is stored isn't specified, but it's values are in table
80 // 14.2.
81
82 // The otherwise unmodified integer registers should be set to 0.
83 for (int index = 0; index < NUM_INTREGS; index++) {
84 tc->setIntReg(index, 0);
85 }
86
87 // These next two loops zero internal microcode and implicit registers.
88 // They aren't specified by the ISA but are used internally by M5's
89 // implementation.

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106 tc->setMiscReg(MISCREG_CR3, 0);
107 tc->setMiscReg(MISCREG_CR4, 0);
108 tc->setMiscReg(MISCREG_CR8, 0);
109
110 tc->setMiscReg(MISCREG_RFLAGS, 0x0000000000000002);
111
112 tc->setMiscReg(MISCREG_EFER, 0);
113
114 for (int seg = 0; seg != NUM_SEGMENTREGS; seg++) {
115 tc->setMiscReg(MISCREG_SEG_SEL(seg), 0);
116 tc->setMiscReg(MISCREG_SEG_BASE(seg), 0);
117 tc->setMiscReg(MISCREG_SEG_LIMIT(seg), 0xffff);
118 tc->setMiscReg(MISCREG_SEG_ATTR(seg), 0);
119 }
120
121 tc->setMiscReg(MISCREG_CS, 0xf000);
122 tc->setMiscReg(MISCREG_CS_BASE, 0x00000000ffff0000);
123 // This has the base value pre-added.
124 tc->setMiscReg(MISCREG_CS_LIMIT, 0xffffffff);
125 tc->setMiscReg(MISCREG_CS_ATTR, 0);
126
127 tc->setPC(0x000000000000fff0 +
128 tc->readMiscReg(MISCREG_CS_BASE));
129 tc->setNextPC(tc->readPC() + sizeof(MachInst));
130
131 tc->setMiscReg(MISCREG_GDTR_BASE, 0);
132 tc->setMiscReg(MISCREG_GDTR_LIMIT, 0xffff);
133

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146
147 // This value should be the family/model/stepping of the processor.
148 // (page 418). It should be consistent with the value from CPUID, but the
149 // actual value probably doesn't matter much.
150 tc->setIntReg(INTREG_RDX, 0);
151
152 // TODO initialize x87, 64 bit, and 128 bit media state
153
154 // TODO Set up MTRRs (page 512)
155
156 // TODO Set up machine check registers (page 515)
157
158 tc->setMiscReg(MISCREG_DR0, 0);
159 tc->setMiscReg(MISCREG_DR1, 0);
160 tc->setMiscReg(MISCREG_DR2, 0);
161 tc->setMiscReg(MISCREG_DR3, 0);
162
163 tc->setMiscReg(MISCREG_DR6, 0x00000000ffff0ff0);
164 tc->setMiscReg(MISCREG_DR7, 0x0000000000000400);
165
166 // TODO Set time stamp counter to 0
167
168 // TODO Set up performance monitoring registers (page 517)
169
170 // TODO Set up the rest of the MSRs (page 507)
171
172 // Invalidate the caches (this should already be done for us)
173
174 // TODO Turn on the APIC. This should be handled elsewhere but it isn't
175 // currently being handled at all.
176
177 // Set the SMRAM base address (SMBASE) to 0x00030000
178}
179
180#endif
181
182void startupCPU(ThreadContext *tc, int cpuId)
183{
184 if (cpuId == 0) {
185 // This is the boot strap processor (BSP). Initialize it to look like

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