tlb.hh (8752:28e899b7dee3) tlb.hh (8768:314eb1e2fa94)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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41#define __ARCH_X86_TLB_HH__
42
43#include <list>
44#include <string>
45#include <vector>
46
47#include "arch/x86/regs/segment.hh"
48#include "arch/x86/pagetable.hh"
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 32 unchanged lines hidden (view full) ---

41#define __ARCH_X86_TLB_HH__
42
43#include <list>
44#include <string>
45#include <vector>
46
47#include "arch/x86/regs/segment.hh"
48#include "arch/x86/pagetable.hh"
49#include "config/full_system.hh"
50#include "mem/mem_object.hh"
51#include "mem/request.hh"
52#include "params/X86TLB.hh"
53#include "sim/fault_fwd.hh"
54#include "sim/sim_object.hh"
55#include "sim/tlb.hh"
56
57class ThreadContext;

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111 bool &delayedResponse, bool timing);
112
113 public:
114
115 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
116 void translateTiming(RequestPtr req, ThreadContext *tc,
117 Translation *translation, Mode mode);
118
49#include "mem/mem_object.hh"
50#include "mem/request.hh"
51#include "params/X86TLB.hh"
52#include "sim/fault_fwd.hh"
53#include "sim/sim_object.hh"
54#include "sim/tlb.hh"
55
56class ThreadContext;

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110 bool &delayedResponse, bool timing);
111
112 public:
113
114 Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
115 void translateTiming(RequestPtr req, ThreadContext *tc,
116 Translation *translation, Mode mode);
117
119#if FULL_SYSTEM
120 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
121 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
122#endif
123
124 TlbEntry * insert(Addr vpn, TlbEntry &entry);
125
126 // Checkpointing
127 virtual void serialize(std::ostream &os);
128 virtual void unserialize(Checkpoint *cp, const std::string &section);
129 };
130}
131
132#endif // __ARCH_X86_TLB_HH__
118 TlbEntry * insert(Addr vpn, TlbEntry &entry);
119
120 // Checkpointing
121 virtual void serialize(std::ostream &os);
122 virtual void unserialize(Checkpoint *cp, const std::string &section);
123 };
124}
125
126#endif // __ARCH_X86_TLB_HH__