tlb.hh (5140:2fd7f8477b4c) | tlb.hh (5236:0050ad4fb3ef) |
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1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 45 unchanged lines hidden (view full) --- 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TLB_HH__ 59#define __ARCH_X86_TLB_HH__ 60 61#include <list> | 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 45 unchanged lines hidden (view full) --- 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TLB_HH__ 59#define __ARCH_X86_TLB_HH__ 60 61#include <list> |
62#include <string> |
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62 63#include "arch/x86/pagetable.hh" 64#include "arch/x86/segmentregs.hh" 65#include "config/full_system.hh" | 63 64#include "arch/x86/pagetable.hh" 65#include "arch/x86/segmentregs.hh" 66#include "config/full_system.hh" |
67#include "mem/mem_object.hh" |
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66#include "mem/request.hh" 67#include "params/X86DTB.hh" 68#include "params/X86ITB.hh" 69#include "sim/faults.hh" 70#include "sim/sim_object.hh" 71 72class ThreadContext; 73class Packet; 74 75namespace X86ISA 76{ 77 static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; 78 | 68#include "mem/request.hh" 69#include "params/X86DTB.hh" 70#include "params/X86ITB.hh" 71#include "sim/faults.hh" 72#include "sim/sim_object.hh" 73 74class ThreadContext; 75class Packet; 76 77namespace X86ISA 78{ 79 static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; 80 |
79 class TLB : public SimObject | 81 class TLB; 82 83 class TLB : public MemObject |
80 { | 84 { |
81#if !FULL_SYSTEM | |
82 protected: 83 friend class FakeITLBFault; 84 friend class FakeDTLBFault; | 85 protected: 86 friend class FakeITLBFault; 87 friend class FakeDTLBFault; |
85#endif | 88 89 System * sys; 90 |
86 public: 87 typedef X86TLBParams Params; 88 TLB(const Params *p); 89 90 void dumpAll(); 91 92 TlbEntry *lookup(Addr va, bool update_lru = true); 93 | 91 public: 92 typedef X86TLBParams Params; 93 TLB(const Params *p); 94 95 void dumpAll(); 96 97 TlbEntry *lookup(Addr va, bool update_lru = true); 98 |
99#if FULL_SYSTEM |
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94 protected: | 100 protected: |
101 class Walker 102 { 103 public: 104 enum State { 105 Ready, 106 Waiting, 107 LongPML4, 108 LongPDP, 109 LongPD, 110 LongPTE, 111 PAEPDP, 112 PAEPD, 113 PAEPTE, 114 PSEPD, 115 PD, 116 PTE 117 }; 118 119 // Act on the current state and determine what to do next. If the 120 // walker has finished updating the TLB, this will return false. 121 bool doNext(PacketPtr read, PacketPtr &write); 122 123 // This does an actual load to feed the walker. If we're in 124 // atomic mode, this will drive the state machine itself until 125 // the TLB is filled. If we're in timing mode, the port getting 126 // a reply will drive the machine using this function which will 127 // return after starting the memory operation. 128 void doMemory(Addr addr); 129 130 // Kick off the state machine. 131 void start(bool _uncachable, Addr _vaddr, Addr cr3, State next) 132 { 133 assert(state == Ready); 134 state = Waiting; 135 nextState = next; 136 // If PAE isn't being used, entries are 4 bytes. Otherwise 137 // they're 8. 138 if (next == PSEPD || next == PD || next == PTE) 139 size = 4; 140 else 141 size = 8; 142 vaddr = _vaddr; 143 uncachable = _uncacheable; 144 buildPacket(cr3); 145 if (state == Enums::timing) { 146 port->sendTiming(&packet); 147 } else if (state == Enums::atomic) { 148 port->sendAtomic(&packet); 149 Addr addr; 150 while(doNext(packet.get<uint64_t>(), addr)) { 151 buildPacket(addr); 152 port->sendAtomic(&packet); 153 } 154 } else { 155 panic("Unrecognized memory system mode.\n"); 156 } 157 }; 158 159 protected: 160 friend class TLB; 161 162 class WalkerPort : public Port 163 { 164 public: 165 WalkerPort(const std::string &_name, Walker * _walker) : 166 Port(_name, _walker->tlb), walker(_walker), 167 packet(NULL), snoopRangeSent(false), retrying(false) 168 {} 169 170 protected: 171 Walker * walker; 172 173 PacketPtr packet; 174 vector<PacketPtr> writes; 175 176 bool snoopRangeSent; 177 bool retrying; 178 179 bool recvTiming(PacketPtr pkt); 180 Tick recvAtomic(PacketPtr pkt); 181 void recvFunctional(PacketPtr pkt); 182 void recvStatusChange(Status status); 183 void recvRetry(); 184 void getDeviceAddressRanges(AddrRangeList &resp, 185 bool &snoop) 186 { 187 resp.clear(); 188 snoop = true; 189 } 190 191 public: 192 bool sendTiming(PacketPtr pkt) 193 { 194 retrying = !Port::sendTiming(pkt); 195 return !retrying; 196 } 197 198 bool blocked() { return retrying; } 199 }; 200 201 friend class WalkerPort; 202 203 WalkerPort port; 204 205 Packet packet; 206 Request request; 207 208 TLB * tlb; 209 210 State state; 211 State nextState; 212 int size; 213 214 Addr vaddr; 215 216 public: 217 Walker(const std::string &_name, TLB * _tlb) : 218 port(_name + "-walker_port", this), 219 packet(&request, ReadExReq, Broadcast), 220 tlb(_tlb), state(Ready), nextState(Ready) 221 { 222 } 223 224 225 }; 226 227 Walker walker; 228#endif 229 230 protected: |
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95 int size; 96 97 TlbEntry * tlb; 98 99 typedef std::list<TlbEntry *> EntryList; 100 EntryList freeList; 101 EntryList entryList; 102 | 231 int size; 232 233 TlbEntry * tlb; 234 235 typedef std::list<TlbEntry *> EntryList; 236 EntryList freeList; 237 EntryList entryList; 238 |
239 Port *getPort(const std::string &if_name, int idx = -1); 240 |
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103 void insert(Addr vpn, TlbEntry &entry); 104 105 void invalidateAll(); 106 107 void invalidateNonGlobal(); 108 109 void demapPage(Addr va); 110 --- 43 unchanged lines hidden --- | 241 void insert(Addr vpn, TlbEntry &entry); 242 243 void invalidateAll(); 244 245 void invalidateNonGlobal(); 246 247 void demapPage(Addr va); 248 --- 43 unchanged lines hidden --- |