1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * 9 * The software must be used only for Non-Commercial Use which means any 10 * use which is NOT directed to receiving any direct monetary 11 * compensation for, or commercial advantage from such use. Illustrative 12 * examples of non-commercial use are academic research, personal study, 13 * teaching, education and corporate research & development. 14 * Illustrative examples of commercial use are distributing products for 15 * commercial advantage and providing services using the software for 16 * commercial advantage. 17 * 18 * If you wish to use this software or functionality therein that may be 19 * covered by patents for commercial use, please contact: 20 * Director of Intellectual Property Licensing 21 * Office of Strategy and Technology 22 * Hewlett-Packard Company 23 * 1501 Page Mill Road 24 * Palo Alto, California 94304 25 * 26 * Redistributions of source code must retain the above copyright notice, 27 * this list of conditions and the following disclaimer. Redistributions 28 * in binary form must reproduce the above copyright notice, this list of 29 * conditions and the following disclaimer in the documentation and/or 30 * other materials provided with the distribution. Neither the name of 31 * the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its 32 * contributors may be used to endorse or promote products derived from 33 * this software without specific prior written permission. No right of 34 * sublicense is granted herewith. Derivatives of the software and 35 * output created using the software may be prepared, but only for 36 * Non-Commercial Uses. Derivatives of the software may be shared with 37 * others provided: (i) the others agree to abide by the list of 38 * conditions herein which includes the Non-Commercial Use restrictions; 39 * and (ii) such Derivatives of the software include the above copyright 40 * notice to acknowledge the contribution from this software where 41 * applicable, this list of conditions and the disclaimer below. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TLB_HH__ 59#define __ARCH_X86_TLB_HH__ 60 61#include <list>
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62#include <vector> |
63#include <string> 64 65#include "arch/x86/pagetable.hh" 66#include "arch/x86/segmentregs.hh" 67#include "config/full_system.hh" 68#include "mem/mem_object.hh" 69#include "mem/request.hh" 70#include "params/X86DTB.hh" 71#include "params/X86ITB.hh" 72#include "sim/faults.hh" 73#include "sim/sim_object.hh" 74 75class ThreadContext; 76class Packet; 77 78namespace X86ISA 79{ 80 static const unsigned StoreCheck = 1 << NUM_SEGMENTREGS; 81 82 class TLB; 83 84 class TLB : public MemObject 85 { 86 protected: 87 friend class FakeITLBFault; 88 friend class FakeDTLBFault; 89 90 System * sys; 91
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92 bool allowNX; 93 |
94 public: 95 typedef X86TLBParams Params; 96 TLB(const Params *p); 97 98 void dumpAll(); 99 100 TlbEntry *lookup(Addr va, bool update_lru = true); 101 102#if FULL_SYSTEM 103 protected: 104 class Walker 105 { 106 public: 107 enum State { 108 Ready, 109 Waiting, 110 LongPML4, 111 LongPDP, 112 LongPD, 113 LongPTE, 114 PAEPDP, 115 PAEPD, 116 PAEPTE, 117 PSEPD, 118 PD, 119 PTE 120 }; 121
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119 // Act on the current state and determine what to do next. If the
120 // walker has finished updating the TLB, this will return false.
121 bool doNext(PacketPtr read, PacketPtr &write);
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122 // Act on the current state and determine what to do next. read 123 // should be the packet that just came back from a read and write 124 // should be NULL. When the function returns, read is either NULL 125 // if the machine is finished, or points to a packet to initiate 126 // the next read. If any write is required to update an "accessed" 127 // bit, write will point to a packet to do the write. Otherwise it 128 // will be NULL. 129 void doNext(PacketPtr &read, PacketPtr &write); |
130
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123 // This does an actual load to feed the walker. If we're in
124 // atomic mode, this will drive the state machine itself until
125 // the TLB is filled. If we're in timing mode, the port getting
126 // a reply will drive the machine using this function which will
127 // return after starting the memory operation.
128 void doMemory(Addr addr);
129
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131 // Kick off the state machine.
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131 void start(bool _uncachable, Addr _vaddr, Addr cr3, State next)
132 {
133 assert(state == Ready);
134 state = Waiting;
135 nextState = next;
136 // If PAE isn't being used, entries are 4 bytes. Otherwise
137 // they're 8.
138 if (next == PSEPD || next == PD || next == PTE)
139 size = 4;
140 else
141 size = 8;
142 vaddr = _vaddr;
143 uncachable = _uncacheable;
144 buildPacket(cr3);
145 if (state == Enums::timing) {
146 port->sendTiming(&packet);
147 } else if (state == Enums::atomic) {
148 port->sendAtomic(&packet);
149 Addr addr;
150 while(doNext(packet.get<uint64_t>(), addr)) {
151 buildPacket(addr);
152 port->sendAtomic(&packet);
153 }
154 } else {
155 panic("Unrecognized memory system mode.\n");
156 }
157 };
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132 void start(ThreadContext * _tc, Addr vaddr); |
133 134 protected: 135 friend class TLB; 136
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137 /* 138 * State having to do with sending packets. 139 */ 140 PacketPtr read; 141 std::vector<PacketPtr> writes; 142 143 // How many memory operations are in flight. 144 unsigned inflight; 145 146 bool retrying; 147 148 /* 149 * Functions for dealing with packets. 150 */ 151 bool recvTiming(PacketPtr pkt); 152 void recvRetry(); 153 154 void sendPackets(); 155 156 /* 157 * Port for accessing memory 158 */ |
159 class WalkerPort : public Port 160 { 161 public: 162 WalkerPort(const std::string &_name, Walker * _walker) : 163 Port(_name, _walker->tlb), walker(_walker),
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167 packet(NULL), snoopRangeSent(false), retrying(false)
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164 snoopRangeSent(false) |
165 {} 166 167 protected: 168 Walker * walker; 169
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173 PacketPtr packet;
174 vector<PacketPtr> writes;
175
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170 bool snoopRangeSent;
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177 bool retrying;
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171 172 bool recvTiming(PacketPtr pkt); 173 Tick recvAtomic(PacketPtr pkt); 174 void recvFunctional(PacketPtr pkt); 175 void recvStatusChange(Status status); 176 void recvRetry(); 177 void getDeviceAddressRanges(AddrRangeList &resp, 178 bool &snoop) 179 { 180 resp.clear(); 181 snoop = true; 182 }
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190
191 public:
192 bool sendTiming(PacketPtr pkt)
193 {
194 retrying = !Port::sendTiming(pkt);
195 return !retrying;
196 }
197
198 bool blocked() { return retrying; }
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183 }; 184 185 friend class WalkerPort; 186 187 WalkerPort port; 188
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205 Packet packet;
206 Request request;
207
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189 // The TLB we're supposed to load. |
190 TLB * tlb; 191
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192 /* 193 * State machine state. 194 */ 195 ThreadContext * tc; |
196 State state; 197 State nextState; 198 int size;
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199 bool enableNX; 200 TlbEntry entry; |
201
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214 Addr vaddr;
215
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202 public: 203 Walker(const std::string &_name, TLB * _tlb) :
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204 read(NULL), inflight(0), retrying(false), |
205 port(_name + "-walker_port", this),
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219 packet(&request, ReadExReq, Broadcast),
220 tlb(_tlb), state(Ready), nextState(Ready)
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206 tlb(_tlb), 207 tc(NULL), state(Ready), nextState(Ready) |
208 { 209 }
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223
224
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210 }; 211 212 Walker walker;
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213 |
214#endif 215
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216 Port *getPort(const std::string &if_name, int idx = -1); 217 |
218 protected: 219 int size; 220 221 TlbEntry * tlb; 222 223 typedef std::list<TlbEntry *> EntryList; 224 EntryList freeList; 225 EntryList entryList; 226
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239 Port *getPort(const std::string &if_name, int idx = -1);
240
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227 void insert(Addr vpn, TlbEntry &entry); 228 229 void invalidateAll(); 230 231 void invalidateNonGlobal(); 232 233 void demapPage(Addr va); 234 235 template<class TlbFault> 236 Fault translate(RequestPtr &req, ThreadContext *tc, 237 bool write, bool execute); 238 239 public: 240 // Checkpointing 241 virtual void serialize(std::ostream &os); 242 virtual void unserialize(Checkpoint *cp, const std::string §ion); 243 }; 244 245 class ITB : public TLB 246 { 247 public: 248 typedef X86ITBParams Params; 249 ITB(const Params *p) : TLB(p) 250 {
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251 sys = p->system; 252 allowNX = false; |
253 } 254 255 Fault translate(RequestPtr &req, ThreadContext *tc); 256 257 friend class DTB; 258 }; 259 260 class DTB : public TLB 261 { 262 public: 263 typedef X86DTBParams Params; 264 DTB(const Params *p) : TLB(p) 265 {
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266 sys = p->system; 267 allowNX = true; |
268 } 269 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 270#if FULL_SYSTEM 271 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 272 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); 273#endif 274 275 // Checkpointing 276 virtual void serialize(std::ostream &os); 277 virtual void unserialize(Checkpoint *cp, const std::string §ion); 278 }; 279} 280 281#endif // __ARCH_X86_TLB_HH__
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