1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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54 *
55 * Authors: Gabe Black
56 */
57
58#ifndef __ARCH_X86_TLB_HH__
59#define __ARCH_X86_TLB_HH__
60
61#include <list>
62#include <vector>
63#include <string>
64
65#include "arch/x86/pagetable.hh"
66#include "arch/x86/segmentregs.hh"
67#include "config/full_system.hh"
68#include "mem/mem_object.hh"
69#include "mem/request.hh"
70#include "params/X86DTB.hh"

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84 class TLB : public MemObject
85 {
86 protected:
87 friend class FakeITLBFault;
88 friend class FakeDTLBFault;
89
90 System * sys;
91
92 bool allowNX;
93
94 public:
95 typedef X86TLBParams Params;
96 TLB(const Params *p);
97
98 void dumpAll();
99
100 TlbEntry *lookup(Addr va, bool update_lru = true);
101

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114 PAEPDP,
115 PAEPD,
116 PAEPTE,
117 PSEPD,
118 PD,
119 PTE
120 };
121
119 // Act on the current state and determine what to do next. If the
120 // walker has finished updating the TLB, this will return false.
121 bool doNext(PacketPtr read, PacketPtr &write);
122 // Act on the current state and determine what to do next. read
123 // should be the packet that just came back from a read and write
124 // should be NULL. When the function returns, read is either NULL
125 // if the machine is finished, or points to a packet to initiate
126 // the next read. If any write is required to update an "accessed"
127 // bit, write will point to a packet to do the write. Otherwise it
128 // will be NULL.
129 void doNext(PacketPtr &read, PacketPtr &write);
130
123 // This does an actual load to feed the walker. If we're in
124 // atomic mode, this will drive the state machine itself until
125 // the TLB is filled. If we're in timing mode, the port getting
126 // a reply will drive the machine using this function which will
127 // return after starting the memory operation.
128 void doMemory(Addr addr);
129
131 // Kick off the state machine.
131 void start(bool _uncachable, Addr _vaddr, Addr cr3, State next)
132 {
133 assert(state == Ready);
134 state = Waiting;
135 nextState = next;
136 // If PAE isn't being used, entries are 4 bytes. Otherwise
137 // they're 8.
138 if (next == PSEPD || next == PD || next == PTE)
139 size = 4;
140 else
141 size = 8;
142 vaddr = _vaddr;
143 uncachable = _uncacheable;
144 buildPacket(cr3);
145 if (state == Enums::timing) {
146 port->sendTiming(&packet);
147 } else if (state == Enums::atomic) {
148 port->sendAtomic(&packet);
149 Addr addr;
150 while(doNext(packet.get<uint64_t>(), addr)) {
151 buildPacket(addr);
152 port->sendAtomic(&packet);
153 }
154 } else {
155 panic("Unrecognized memory system mode.\n");
156 }
157 };
132 void start(ThreadContext * _tc, Addr vaddr);
133
134 protected:
135 friend class TLB;
136
137 /*
138 * State having to do with sending packets.
139 */
140 PacketPtr read;
141 std::vector<PacketPtr> writes;
142
143 // How many memory operations are in flight.
144 unsigned inflight;
145
146 bool retrying;
147
148 /*
149 * Functions for dealing with packets.
150 */
151 bool recvTiming(PacketPtr pkt);
152 void recvRetry();
153
154 void sendPackets();
155
156 /*
157 * Port for accessing memory
158 */
159 class WalkerPort : public Port
160 {
161 public:
162 WalkerPort(const std::string &_name, Walker * _walker) :
163 Port(_name, _walker->tlb), walker(_walker),
167 packet(NULL), snoopRangeSent(false), retrying(false)
164 snoopRangeSent(false)
165 {}
166
167 protected:
168 Walker * walker;
169
173 PacketPtr packet;
174 vector<PacketPtr> writes;
175
170 bool snoopRangeSent;
177 bool retrying;
171
172 bool recvTiming(PacketPtr pkt);
173 Tick recvAtomic(PacketPtr pkt);
174 void recvFunctional(PacketPtr pkt);
175 void recvStatusChange(Status status);
176 void recvRetry();
177 void getDeviceAddressRanges(AddrRangeList &resp,
178 bool &snoop)
179 {
180 resp.clear();
181 snoop = true;
182 }
190
191 public:
192 bool sendTiming(PacketPtr pkt)
193 {
194 retrying = !Port::sendTiming(pkt);
195 return !retrying;
196 }
197
198 bool blocked() { return retrying; }
183 };
184
185 friend class WalkerPort;
186
187 WalkerPort port;
188
205 Packet packet;
206 Request request;
207
189 // The TLB we're supposed to load.
190 TLB * tlb;
191
192 /*
193 * State machine state.
194 */
195 ThreadContext * tc;
196 State state;
197 State nextState;
198 int size;
199 bool enableNX;
200 TlbEntry entry;
201
214 Addr vaddr;
215
202 public:
203 Walker(const std::string &_name, TLB * _tlb) :
204 read(NULL), inflight(0), retrying(false),
205 port(_name + "-walker_port", this),
219 packet(&request, ReadExReq, Broadcast),
220 tlb(_tlb), state(Ready), nextState(Ready)
206 tlb(_tlb),
207 tc(NULL), state(Ready), nextState(Ready)
208 {
209 }
223
224
210 };
211
212 Walker walker;
213
214#endif
215
216 Port *getPort(const std::string &if_name, int idx = -1);
217
218 protected:
219 int size;
220
221 TlbEntry * tlb;
222
223 typedef std::list<TlbEntry *> EntryList;
224 EntryList freeList;
225 EntryList entryList;
226
239 Port *getPort(const std::string &if_name, int idx = -1);
240
227 void insert(Addr vpn, TlbEntry &entry);
228
229 void invalidateAll();
230
231 void invalidateNonGlobal();
232
233 void demapPage(Addr va);
234

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243 };
244
245 class ITB : public TLB
246 {
247 public:
248 typedef X86ITBParams Params;
249 ITB(const Params *p) : TLB(p)
250 {
251 sys = p->system;
252 allowNX = false;
253 }
254
255 Fault translate(RequestPtr &req, ThreadContext *tc);
256
257 friend class DTB;
258 };
259
260 class DTB : public TLB
261 {
262 public:
263 typedef X86DTBParams Params;
264 DTB(const Params *p) : TLB(p)
265 {
266 sys = p->system;
267 allowNX = true;
268 }
269 Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
270#if FULL_SYSTEM
271 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
272 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
273#endif
274
275 // Checkpointing
276 virtual void serialize(std::ostream &os);
277 virtual void unserialize(Checkpoint *cp, const std::string &section);
278 };
279}
280
281#endif // __ARCH_X86_TLB_HH__