tlb.hh (5236:0050ad4fb3ef) | tlb.hh (5237:6c819dbe8045) |
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1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 45 unchanged lines hidden (view full) --- 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TLB_HH__ 59#define __ARCH_X86_TLB_HH__ 60 61#include <list> | 1/* 2 * Copyright (c) 2007 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * Redistribution and use of this software in source and binary forms, 6 * with or without modification, are permitted provided that the 7 * following conditions are met: 8 * --- 45 unchanged lines hidden (view full) --- 54 * 55 * Authors: Gabe Black 56 */ 57 58#ifndef __ARCH_X86_TLB_HH__ 59#define __ARCH_X86_TLB_HH__ 60 61#include <list> |
62#include <vector> |
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62#include <string> 63 64#include "arch/x86/pagetable.hh" 65#include "arch/x86/segmentregs.hh" 66#include "config/full_system.hh" 67#include "mem/mem_object.hh" 68#include "mem/request.hh" 69#include "params/X86DTB.hh" --- 13 unchanged lines hidden (view full) --- 83 class TLB : public MemObject 84 { 85 protected: 86 friend class FakeITLBFault; 87 friend class FakeDTLBFault; 88 89 System * sys; 90 | 63#include <string> 64 65#include "arch/x86/pagetable.hh" 66#include "arch/x86/segmentregs.hh" 67#include "config/full_system.hh" 68#include "mem/mem_object.hh" 69#include "mem/request.hh" 70#include "params/X86DTB.hh" --- 13 unchanged lines hidden (view full) --- 84 class TLB : public MemObject 85 { 86 protected: 87 friend class FakeITLBFault; 88 friend class FakeDTLBFault; 89 90 System * sys; 91 |
92 bool allowNX; 93 |
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91 public: 92 typedef X86TLBParams Params; 93 TLB(const Params *p); 94 95 void dumpAll(); 96 97 TlbEntry *lookup(Addr va, bool update_lru = true); 98 --- 12 unchanged lines hidden (view full) --- 111 PAEPDP, 112 PAEPD, 113 PAEPTE, 114 PSEPD, 115 PD, 116 PTE 117 }; 118 | 94 public: 95 typedef X86TLBParams Params; 96 TLB(const Params *p); 97 98 void dumpAll(); 99 100 TlbEntry *lookup(Addr va, bool update_lru = true); 101 --- 12 unchanged lines hidden (view full) --- 114 PAEPDP, 115 PAEPD, 116 PAEPTE, 117 PSEPD, 118 PD, 119 PTE 120 }; 121 |
119 // Act on the current state and determine what to do next. If the 120 // walker has finished updating the TLB, this will return false. 121 bool doNext(PacketPtr read, PacketPtr &write); | 122 // Act on the current state and determine what to do next. read 123 // should be the packet that just came back from a read and write 124 // should be NULL. When the function returns, read is either NULL 125 // if the machine is finished, or points to a packet to initiate 126 // the next read. If any write is required to update an "accessed" 127 // bit, write will point to a packet to do the write. Otherwise it 128 // will be NULL. 129 void doNext(PacketPtr &read, PacketPtr &write); |
122 | 130 |
123 // This does an actual load to feed the walker. If we're in 124 // atomic mode, this will drive the state machine itself until 125 // the TLB is filled. If we're in timing mode, the port getting 126 // a reply will drive the machine using this function which will 127 // return after starting the memory operation. 128 void doMemory(Addr addr); 129 | |
130 // Kick off the state machine. | 131 // Kick off the state machine. |
131 void start(bool _uncachable, Addr _vaddr, Addr cr3, State next) 132 { 133 assert(state == Ready); 134 state = Waiting; 135 nextState = next; 136 // If PAE isn't being used, entries are 4 bytes. Otherwise 137 // they're 8. 138 if (next == PSEPD || next == PD || next == PTE) 139 size = 4; 140 else 141 size = 8; 142 vaddr = _vaddr; 143 uncachable = _uncacheable; 144 buildPacket(cr3); 145 if (state == Enums::timing) { 146 port->sendTiming(&packet); 147 } else if (state == Enums::atomic) { 148 port->sendAtomic(&packet); 149 Addr addr; 150 while(doNext(packet.get<uint64_t>(), addr)) { 151 buildPacket(addr); 152 port->sendAtomic(&packet); 153 } 154 } else { 155 panic("Unrecognized memory system mode.\n"); 156 } 157 }; | 132 void start(ThreadContext * _tc, Addr vaddr); |
158 159 protected: 160 friend class TLB; 161 | 133 134 protected: 135 friend class TLB; 136 |
137 /* 138 * State having to do with sending packets. 139 */ 140 PacketPtr read; 141 std::vector<PacketPtr> writes; 142 143 // How many memory operations are in flight. 144 unsigned inflight; 145 146 bool retrying; 147 148 /* 149 * Functions for dealing with packets. 150 */ 151 bool recvTiming(PacketPtr pkt); 152 void recvRetry(); 153 154 void sendPackets(); 155 156 /* 157 * Port for accessing memory 158 */ |
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162 class WalkerPort : public Port 163 { 164 public: 165 WalkerPort(const std::string &_name, Walker * _walker) : 166 Port(_name, _walker->tlb), walker(_walker), | 159 class WalkerPort : public Port 160 { 161 public: 162 WalkerPort(const std::string &_name, Walker * _walker) : 163 Port(_name, _walker->tlb), walker(_walker), |
167 packet(NULL), snoopRangeSent(false), retrying(false) | 164 snoopRangeSent(false) |
168 {} 169 170 protected: 171 Walker * walker; 172 | 165 {} 166 167 protected: 168 Walker * walker; 169 |
173 PacketPtr packet; 174 vector<PacketPtr> writes; 175 | |
176 bool snoopRangeSent; | 170 bool snoopRangeSent; |
177 bool retrying; | |
178 179 bool recvTiming(PacketPtr pkt); 180 Tick recvAtomic(PacketPtr pkt); 181 void recvFunctional(PacketPtr pkt); 182 void recvStatusChange(Status status); 183 void recvRetry(); 184 void getDeviceAddressRanges(AddrRangeList &resp, 185 bool &snoop) 186 { 187 resp.clear(); 188 snoop = true; 189 } | 171 172 bool recvTiming(PacketPtr pkt); 173 Tick recvAtomic(PacketPtr pkt); 174 void recvFunctional(PacketPtr pkt); 175 void recvStatusChange(Status status); 176 void recvRetry(); 177 void getDeviceAddressRanges(AddrRangeList &resp, 178 bool &snoop) 179 { 180 resp.clear(); 181 snoop = true; 182 } |
190 191 public: 192 bool sendTiming(PacketPtr pkt) 193 { 194 retrying = !Port::sendTiming(pkt); 195 return !retrying; 196 } 197 198 bool blocked() { return retrying; } | |
199 }; 200 201 friend class WalkerPort; 202 203 WalkerPort port; 204 | 183 }; 184 185 friend class WalkerPort; 186 187 WalkerPort port; 188 |
205 Packet packet; 206 Request request; 207 | 189 // The TLB we're supposed to load. |
208 TLB * tlb; 209 | 190 TLB * tlb; 191 |
192 /* 193 * State machine state. 194 */ 195 ThreadContext * tc; |
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210 State state; 211 State nextState; 212 int size; | 196 State state; 197 State nextState; 198 int size; |
199 bool enableNX; 200 TlbEntry entry; |
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213 | 201 |
214 Addr vaddr; 215 | |
216 public: 217 Walker(const std::string &_name, TLB * _tlb) : | 202 public: 203 Walker(const std::string &_name, TLB * _tlb) : |
204 read(NULL), inflight(0), retrying(false), |
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218 port(_name + "-walker_port", this), | 205 port(_name + "-walker_port", this), |
219 packet(&request, ReadExReq, Broadcast), 220 tlb(_tlb), state(Ready), nextState(Ready) | 206 tlb(_tlb), 207 tc(NULL), state(Ready), nextState(Ready) |
221 { 222 } | 208 { 209 } |
223 224 | |
225 }; 226 227 Walker walker; | 210 }; 211 212 Walker walker; |
213 |
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228#endif 229 | 214#endif 215 |
216 Port *getPort(const std::string &if_name, int idx = -1); 217 |
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230 protected: 231 int size; 232 233 TlbEntry * tlb; 234 235 typedef std::list<TlbEntry *> EntryList; 236 EntryList freeList; 237 EntryList entryList; 238 | 218 protected: 219 int size; 220 221 TlbEntry * tlb; 222 223 typedef std::list<TlbEntry *> EntryList; 224 EntryList freeList; 225 EntryList entryList; 226 |
239 Port *getPort(const std::string &if_name, int idx = -1); 240 | |
241 void insert(Addr vpn, TlbEntry &entry); 242 243 void invalidateAll(); 244 245 void invalidateNonGlobal(); 246 247 void demapPage(Addr va); 248 --- 8 unchanged lines hidden (view full) --- 257 }; 258 259 class ITB : public TLB 260 { 261 public: 262 typedef X86ITBParams Params; 263 ITB(const Params *p) : TLB(p) 264 { | 227 void insert(Addr vpn, TlbEntry &entry); 228 229 void invalidateAll(); 230 231 void invalidateNonGlobal(); 232 233 void demapPage(Addr va); 234 --- 8 unchanged lines hidden (view full) --- 243 }; 244 245 class ITB : public TLB 246 { 247 public: 248 typedef X86ITBParams Params; 249 ITB(const Params *p) : TLB(p) 250 { |
251 sys = p->system; 252 allowNX = false; |
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265 } 266 267 Fault translate(RequestPtr &req, ThreadContext *tc); 268 269 friend class DTB; 270 }; 271 272 class DTB : public TLB 273 { 274 public: 275 typedef X86DTBParams Params; 276 DTB(const Params *p) : TLB(p) 277 { | 253 } 254 255 Fault translate(RequestPtr &req, ThreadContext *tc); 256 257 friend class DTB; 258 }; 259 260 class DTB : public TLB 261 { 262 public: 263 typedef X86DTBParams Params; 264 DTB(const Params *p) : TLB(p) 265 { |
266 sys = p->system; 267 allowNX = true; |
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278 } 279 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 280#if FULL_SYSTEM 281 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 282 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); 283#endif 284 285 // Checkpointing 286 virtual void serialize(std::ostream &os); 287 virtual void unserialize(Checkpoint *cp, const std::string §ion); 288 }; 289} 290 291#endif // __ARCH_X86_TLB_HH__ | 268 } 269 Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 270#if FULL_SYSTEM 271 Tick doMmuRegRead(ThreadContext *tc, Packet *pkt); 272 Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt); 273#endif 274 275 // Checkpointing 276 virtual void serialize(std::ostream &os); 277 virtual void unserialize(Checkpoint *cp, const std::string §ion); 278 }; 279} 280 281#endif // __ARCH_X86_TLB_HH__ |