tlb.cc (9818:ebd7d3e04b5f) tlb.cc (9898:2935441b0870)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/generic/mmapped_ipr.hh"
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/regs/msr.hh"
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/pagetable_walker.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"

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232
233 // Check for an access to the local APIC
234 if (FullSystem) {
235 LocalApicBase localApicBase =
236 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
237 AddrRange apicRange(localApicBase.base * PageBytes,
238 (localApicBase.base + 1) * PageBytes - 1);
239
43#include "arch/x86/insts/microldstop.hh"
44#include "arch/x86/regs/misc.hh"
45#include "arch/x86/regs/msr.hh"
46#include "arch/x86/faults.hh"
47#include "arch/x86/pagetable.hh"
48#include "arch/x86/pagetable_walker.hh"
49#include "arch/x86/tlb.hh"
50#include "arch/x86/x86_traits.hh"

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233
234 // Check for an access to the local APIC
235 if (FullSystem) {
236 LocalApicBase localApicBase =
237 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
238 AddrRange apicRange(localApicBase.base * PageBytes,
239 (localApicBase.base + 1) * PageBytes - 1);
240
241 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
242
240 if (apicRange.contains(paddr)) {
241 // The Intel developer's manuals say the below restrictions apply,
242 // but the linux kernel, because of a compiler optimization, breaks
243 // them.
244 /*
245 // Check alignment
246 if (paddr & ((32/8) - 1))
247 return new GeneralProtection(0);
248 // Check access size
249 if (req->getSize() != (32/8))
250 return new GeneralProtection(0);
251 */
252 // Force the access to be uncacheable.
253 req->setFlags(Request::UNCACHEABLE);
254 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
255 paddr - apicRange.start()));
243 if (apicRange.contains(paddr)) {
244 // The Intel developer's manuals say the below restrictions apply,
245 // but the linux kernel, because of a compiler optimization, breaks
246 // them.
247 /*
248 // Check alignment
249 if (paddr & ((32/8) - 1))
250 return new GeneralProtection(0);
251 // Check access size
252 if (req->getSize() != (32/8))
253 return new GeneralProtection(0);
254 */
255 // Force the access to be uncacheable.
256 req->setFlags(Request::UNCACHEABLE);
257 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
258 paddr - apicRange.start()));
259 } else if (m5opRange.contains(paddr)) {
260 req->setFlags(Request::MMAPPED_IPR);
261 req->setPaddr(GenericISA::iprAddressPseudoInst(
262 (paddr >> 8) & 0xFF,
263 paddr & 0xFF));
256 }
257 }
258
259 return NoFault;
260}
261
262Fault
263TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,

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265 }
266
267 return NoFault;
268}
269
270Fault
271TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,

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