tlb.cc (9423:43caa4ca5979) tlb.cc (9738:304a37519d11)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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221 return NoFault;
222 } else {
223 panic("Access to unrecognized internal address space %#x.\n",
224 prefix);
225 }
226}
227
228Fault
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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221 return NoFault;
222 } else {
223 panic("Access to unrecognized internal address space %#x.\n",
224 prefix);
225 }
226}
227
228Fault
229TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
230{
231 Addr paddr = req->getPaddr();
232
233 // Check for an access to the local APIC
234 if (FullSystem) {
235 LocalApicBase localApicBase =
236 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
237 AddrRange apicRange(localApicBase.base * PageBytes,
238 (localApicBase.base + 1) * PageBytes - 1);
239
240 if (apicRange.contains(paddr)) {
241 // The Intel developer's manuals say the below restrictions apply,
242 // but the linux kernel, because of a compiler optimization, breaks
243 // them.
244 /*
245 // Check alignment
246 if (paddr & ((32/8) - 1))
247 return new GeneralProtection(0);
248 // Check access size
249 if (req->getSize() != (32/8))
250 return new GeneralProtection(0);
251 */
252 // Force the access to be uncacheable.
253 req->setFlags(Request::UNCACHEABLE);
254 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
255 paddr - apicRange.start()));
256 }
257 }
258
259 return NoFault;
260}
261
262Fault
229TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
230 Mode mode, bool &delayedResponse, bool timing)
231{
232 uint32_t flags = req->getFlags();
233 int seg = flags & SegmentFlagMask;
234 bool storeCheck = flags & (StoreCheck << FlagShift);
235
236 delayedResponse = false;

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361 req->setPaddr(vaddr);
362 }
363 } else {
364 // Real mode
365 DPRINTF(TLB, "In real mode.\n");
366 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
367 req->setPaddr(vaddr);
368 }
263TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
264 Mode mode, bool &delayedResponse, bool timing)
265{
266 uint32_t flags = req->getFlags();
267 int seg = flags & SegmentFlagMask;
268 bool storeCheck = flags & (StoreCheck << FlagShift);
269
270 delayedResponse = false;

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395 req->setPaddr(vaddr);
396 }
397 } else {
398 // Real mode
399 DPRINTF(TLB, "In real mode.\n");
400 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
401 req->setPaddr(vaddr);
402 }
369 // Check for an access to the local APIC
370 if (FullSystem) {
371 LocalApicBase localApicBase =
372 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
373 Addr baseAddr = localApicBase.base * PageBytes;
374 Addr paddr = req->getPaddr();
375 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
376 // The Intel developer's manuals say the below restrictions apply,
377 // but the linux kernel, because of a compiler optimization, breaks
378 // them.
379 /*
380 // Check alignment
381 if (paddr & ((32/8) - 1))
382 return new GeneralProtection(0);
383 // Check access size
384 if (req->getSize() != (32/8))
385 return new GeneralProtection(0);
386 */
387 // Force the access to be uncacheable.
388 req->setFlags(Request::UNCACHEABLE);
389 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
390 paddr - baseAddr));
391 }
392 }
393 return NoFault;
403
404 return finalizePhysical(req, tc, mode);
394}
395
396Fault
397TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
398{
399 bool delayedResponse;
400 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
401}

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406
407Fault
408TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
409{
410 bool delayedResponse;
411 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
412}

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