tlb.cc (8768:314eb1e2fa94) tlb.cc (8797:3202eb01e01e)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 308 unchanged lines hidden (view full) ---

317 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
318 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
319 newEntry.pageStart());
320 entry = insert(alignedVaddr, newEntry);
321 }
322 DPRINTF(TLB, "Miss was serviced.\n");
323 }
324 }
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 308 unchanged lines hidden (view full) ---

317 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
318 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
319 newEntry.pageStart());
320 entry = insert(alignedVaddr, newEntry);
321 }
322 DPRINTF(TLB, "Miss was serviced.\n");
323 }
324 }
325
326 DPRINTF(TLB, "Entry found with paddr %#x, "
327 "doing protection checks.\n", entry->paddr);
325 // Do paging protection checks.
326 bool inUser = (m5Reg.cpl == 3 &&
327 !(flags & (CPL0FlagBit << FlagShift)));
328 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
329 bool badWrite = (!entry->writable && (inUser || cr0.wp));
330 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
331 // The page must have been present to get into the TLB in
332 // the first place. We'll assume the reserved bits are
333 // fine even though we're not checking them.
334 return new PageFault(vaddr, true, mode, inUser, false);
335 }
336 if (storeCheck && badWrite) {
337 // This would fault if this were a write, so return a page
338 // fault that reflects that happening.
339 return new PageFault(vaddr, true, Write, inUser, false);
340 }
341
328 // Do paging protection checks.
329 bool inUser = (m5Reg.cpl == 3 &&
330 !(flags & (CPL0FlagBit << FlagShift)));
331 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
332 bool badWrite = (!entry->writable && (inUser || cr0.wp));
333 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
334 // The page must have been present to get into the TLB in
335 // the first place. We'll assume the reserved bits are
336 // fine even though we're not checking them.
337 return new PageFault(vaddr, true, mode, inUser, false);
338 }
339 if (storeCheck && badWrite) {
340 // This would fault if this were a write, so return a page
341 // fault that reflects that happening.
342 return new PageFault(vaddr, true, Write, inUser, false);
343 }
344
342
343 DPRINTF(TLB, "Entry found with paddr %#x, "
344 "doing protection checks.\n", entry->paddr);
345 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
346 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
347 req->setPaddr(paddr);
348 if (entry->uncacheable)
349 req->setFlags(Request::UNCACHEABLE);
350 } else {
351 //Use the address which already has segmentation applied.
352 DPRINTF(TLB, "Paging disabled.\n");

--- 78 unchanged lines hidden --- 		345 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
346 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
347 req->setPaddr(paddr);
348 if (entry->uncacheable)
349 req->setFlags(Request::UNCACHEABLE);
350 } else {
351 //Use the address which already has segmentation applied.
352 DPRINTF(TLB, "Paging disabled.\n");

--- 78 unchanged lines hidden ---