tlb.cc (8767:e575781f71b8) tlb.cc (8768:314eb1e2fa94)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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44#include "arch/x86/regs/msr.hh"
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/pagetable_walker.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 35 unchanged lines hidden (view full) ---

44#include "arch/x86/regs/msr.hh"
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/pagetable_walker.hh"
48#include "arch/x86/tlb.hh"
49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
52#include "config/full_system.hh"
53#include "cpu/base.hh"
54#include "cpu/thread_context.hh"
55#include "debug/TLB.hh"
56#include "mem/packet_access.hh"
57#include "mem/page_table.hh"
58#include "mem/request.hh"
59#include "sim/full_system.hh"
60#include "sim/process.hh"

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401 bool delayedResponse;
402 assert(translation);
403 Fault fault =
404 TLB::translate(req, tc, translation, mode, delayedResponse, true);
405 if (!delayedResponse)
406 translation->finish(fault, req, tc, mode);
407}
408
52#include "cpu/base.hh"
53#include "cpu/thread_context.hh"
54#include "debug/TLB.hh"
55#include "mem/packet_access.hh"
56#include "mem/page_table.hh"
57#include "mem/request.hh"
58#include "sim/full_system.hh"
59#include "sim/process.hh"

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400 bool delayedResponse;
401 assert(translation);
402 Fault fault =
403 TLB::translate(req, tc, translation, mode, delayedResponse, true);
404 if (!delayedResponse)
405 translation->finish(fault, req, tc, mode);
406}
407
409#if FULL_SYSTEM
410
411Tick
412TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
413{
414 return tc->getCpuPtr()->ticks(1);
415}
416
417Tick
418TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
419{
420 return tc->getCpuPtr()->ticks(1);
421}
422
423Walker *
424TLB::getWalker()
425{
426 return walker;
427}
428
408Walker *
409TLB::getWalker()
410{
411 return walker;
412}
413
429#endif
430
431void
432TLB::serialize(std::ostream &os)
433{
434}
435
436void
437TLB::unserialize(Checkpoint *cp, const std::string &section)
438{
439}
440
441} // namespace X86ISA
442
443X86ISA::TLB *
444X86TLBParams::create()
445{
446 return new X86ISA::TLB(this);
447}
414void
415TLB::serialize(std::ostream &os)
416{
417}
418
419void
420TLB::unserialize(Checkpoint *cp, const std::string &section)
421{
422}
423
424} // namespace X86ISA
425
426X86ISA::TLB *
427X86TLBParams::create()
428{
429 return new X86ISA::TLB(this);
430}