tlb.cc (8752:28e899b7dee3) tlb.cc (8767:e575781f71b8)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
52#include "config/full_system.hh"
53#include "cpu/base.hh"
54#include "cpu/thread_context.hh"
55#include "debug/TLB.hh"
56#include "mem/packet_access.hh"
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include "arch/x86/x86_traits.hh"
50#include "base/bitfield.hh"
51#include "base/trace.hh"
52#include "config/full_system.hh"
53#include "cpu/base.hh"
54#include "cpu/thread_context.hh"
55#include "debug/TLB.hh"
56#include "mem/packet_access.hh"
57#include "mem/request.hh"
58
59#if !FULL_SYSTEM
60#include "mem/page_table.hh"
57#include "mem/page_table.hh"
58#include "mem/request.hh"
59#include "sim/full_system.hh"
61#include "sim/process.hh"
60#include "sim/process.hh"
62#endif
63
61
64#include "sim/full_system.hh"
65
66namespace X86ISA {
67
68TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
69{
70 tlb = new TlbEntry[size];
71 std::memset(tlb, 0, sizeof(TlbEntry) * size);
72
73 for (int x = 0; x < size; x++)

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297 if (timing || fault != NoFault) {
298 // This gets ignored in atomic mode.
299 delayedResponse = true;
300 return fault;
301 }
302 entry = lookup(vaddr);
303 assert(entry);
304 } else {
62namespace X86ISA {
63
64TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size)
65{
66 tlb = new TlbEntry[size];
67 std::memset(tlb, 0, sizeof(TlbEntry) * size);
68
69 for (int x = 0; x < size; x++)

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293 if (timing || fault != NoFault) {
294 // This gets ignored in atomic mode.
295 delayedResponse = true;
296 return fault;
297 }
298 entry = lookup(vaddr);
299 assert(entry);
300 } else {
305#if !FULL_SYSTEM
306 DPRINTF(TLB, "Handling a TLB miss for "
307 "address %#x at pc %#x.\n",
308 vaddr, tc->instAddr());
309
310 Process *p = tc->getProcessPtr();
311 TlbEntry newEntry;
312 bool success = p->pTable->lookup(vaddr, newEntry);
313 if (!success && mode != Execute) {

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321 return new PageFault(vaddr, true, mode, true, false);
322 } else {
323 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
324 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
325 newEntry.pageStart());
326 entry = insert(alignedVaddr, newEntry);
327 }
328 DPRINTF(TLB, "Miss was serviced.\n");
301 DPRINTF(TLB, "Handling a TLB miss for "
302 "address %#x at pc %#x.\n",
303 vaddr, tc->instAddr());
304
305 Process *p = tc->getProcessPtr();
306 TlbEntry newEntry;
307 bool success = p->pTable->lookup(vaddr, newEntry);
308 if (!success && mode != Execute) {

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316 return new PageFault(vaddr, true, mode, true, false);
317 } else {
318 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
319 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
320 newEntry.pageStart());
321 entry = insert(alignedVaddr, newEntry);
322 }
323 DPRINTF(TLB, "Miss was serviced.\n");
329#endif
330 }
331 }
332 // Do paging protection checks.
333 bool inUser = (m5Reg.cpl == 3 &&
334 !(flags & (CPL0FlagBit << FlagShift)));
335 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
336 bool badWrite = (!entry->writable && (inUser || cr0.wp));
337 if ((inUser && !entry->user) || (mode == Write && badWrite)) {

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362 }
363 } else {
364 // Real mode
365 DPRINTF(TLB, "In real mode.\n");
366 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
367 req->setPaddr(vaddr);
368 }
369 // Check for an access to the local APIC
324 }
325 }
326 // Do paging protection checks.
327 bool inUser = (m5Reg.cpl == 3 &&
328 !(flags & (CPL0FlagBit << FlagShift)));
329 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
330 bool badWrite = (!entry->writable && (inUser || cr0.wp));
331 if ((inUser && !entry->user) || (mode == Write && badWrite)) {

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356 }
357 } else {
358 // Real mode
359 DPRINTF(TLB, "In real mode.\n");
360 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
361 req->setPaddr(vaddr);
362 }
363 // Check for an access to the local APIC
370#if FULL_SYSTEM
371 LocalApicBase localApicBase = tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
372 Addr baseAddr = localApicBase.base * PageBytes;
373 Addr paddr = req->getPaddr();
374 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
375 // The Intel developer's manuals say the below restrictions apply,
376 // but the linux kernel, because of a compiler optimization, breaks
377 // them.
378 /*
379 // Check alignment
380 if (paddr & ((32/8) - 1))
381 return new GeneralProtection(0);
382 // Check access size
383 if (req->getSize() != (32/8))
384 return new GeneralProtection(0);
385 */
386 // Force the access to be uncacheable.
387 req->setFlags(Request::UNCACHEABLE);
388 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
364 if (FullSystem) {
365 LocalApicBase localApicBase =
366 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
367 Addr baseAddr = localApicBase.base * PageBytes;
368 Addr paddr = req->getPaddr();
369 if (baseAddr <= paddr && baseAddr + PageBytes > paddr) {
370 // The Intel developer's manuals say the below restrictions apply,
371 // but the linux kernel, because of a compiler optimization, breaks
372 // them.
373 /*
374 // Check alignment
375 if (paddr & ((32/8) - 1))
376 return new GeneralProtection(0);
377 // Check access size
378 if (req->getSize() != (32/8))
379 return new GeneralProtection(0);
380 */
381 // Force the access to be uncacheable.
382 req->setFlags(Request::UNCACHEABLE);
383 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
384 paddr - baseAddr));
385 }
389 }
386 }
390#endif
391 return NoFault;
392};
393
394Fault
395TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
396{
397 bool delayedResponse;
398 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);

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388};
389
390Fault
391TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
392{
393 bool delayedResponse;
394 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);

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