tlb.cc (8582:dd79a696b91c) tlb.cc (8646:ef6cbf0f14dc)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 314 unchanged lines hidden (view full) ---

323 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
324 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
325 newEntry.pageStart());
326 entry = insert(alignedVaddr, newEntry);
327 }
328 DPRINTF(TLB, "Miss was serviced.\n");
329#endif
330 }
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 314 unchanged lines hidden (view full) ---

323 Addr alignedVaddr = p->pTable->pageAlign(vaddr);
324 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
325 newEntry.pageStart());
326 entry = insert(alignedVaddr, newEntry);
327 }
328 DPRINTF(TLB, "Miss was serviced.\n");
329#endif
330 }
331
332 DPRINTF(TLB, "Entry found with paddr %#x, "
333 "doing protection checks.\n", entry->paddr);
331 // Do paging protection checks.
332 bool inUser = (m5Reg.cpl == 3 &&
333 !(flags & (CPL0FlagBit << FlagShift)));
334 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
335 bool badWrite = (!entry->writable && (inUser || cr0.wp));
336 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
337 // The page must have been present to get into the TLB in
338 // the first place. We'll assume the reserved bits are
339 // fine even though we're not checking them.
340 return new PageFault(vaddr, true, mode, inUser, false);
341 }
342 if (storeCheck && badWrite) {
343 // This would fault if this were a write, so return a page
344 // fault that reflects that happening.
345 return new PageFault(vaddr, true, Write, inUser, false);
346 }
347
334 // Do paging protection checks.
335 bool inUser = (m5Reg.cpl == 3 &&
336 !(flags & (CPL0FlagBit << FlagShift)));
337 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
338 bool badWrite = (!entry->writable && (inUser || cr0.wp));
339 if ((inUser && !entry->user) || (mode == Write && badWrite)) {
340 // The page must have been present to get into the TLB in
341 // the first place. We'll assume the reserved bits are
342 // fine even though we're not checking them.
343 return new PageFault(vaddr, true, mode, inUser, false);
344 }
345 if (storeCheck && badWrite) {
346 // This would fault if this were a write, so return a page
347 // fault that reflects that happening.
348 return new PageFault(vaddr, true, Write, inUser, false);
349 }
350
348
349 DPRINTF(TLB, "Entry found with paddr %#x, "
350 "doing protection checks.\n", entry->paddr);
351 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
352 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
353 req->setPaddr(paddr);
354 if (entry->uncacheable)
355 req->setFlags(Request::UNCACHEABLE);
356 } else {
357 //Use the address which already has segmentation applied.
358 DPRINTF(TLB, "Paging disabled.\n");

--- 92 unchanged lines hidden --- 		351 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
352 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
353 req->setPaddr(paddr);
354 if (entry->uncacheable)
355 req->setFlags(Request::UNCACHEABLE);
356 } else {
357 //Use the address which already has segmentation applied.
358 DPRINTF(TLB, "Paging disabled.\n");

--- 92 unchanged lines hidden ---