tlb.cc (8539:7d3ea3c65c66) tlb.cc (8582:dd79a696b91c)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 27 unchanged lines hidden (view full) ---

36 *
37 * Authors: Gabe Black
38 */
39
40#include <cstring>
41
42#include "arch/x86/insts/microldstop.hh"
43#include "arch/x86/regs/misc.hh"
44#include "arch/x86/regs/msr.hh"
44#include "arch/x86/faults.hh"
45#include "arch/x86/pagetable.hh"
46#include "arch/x86/tlb.hh"
47#include "arch/x86/x86_traits.hh"
48#include "base/bitfield.hh"
49#include "base/trace.hh"
50#include "config/full_system.hh"
51#include "cpu/base.hh"

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172TLB::translateInt(RequestPtr req, ThreadContext *tc)
173{
174 DPRINTF(TLB, "Addresses references internal memory.\n");
175 Addr vaddr = req->getVaddr();
176 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
177 if (prefix == IntAddrPrefixCPUID) {
178 panic("CPUID memory space not yet implemented!\n");
179 } else if (prefix == IntAddrPrefixMSR) {
45#include "arch/x86/faults.hh"
46#include "arch/x86/pagetable.hh"
47#include "arch/x86/tlb.hh"
48#include "arch/x86/x86_traits.hh"
49#include "base/bitfield.hh"
50#include "base/trace.hh"
51#include "config/full_system.hh"
52#include "cpu/base.hh"

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173TLB::translateInt(RequestPtr req, ThreadContext *tc)
174{
175 DPRINTF(TLB, "Addresses references internal memory.\n");
176 Addr vaddr = req->getVaddr();
177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
178 if (prefix == IntAddrPrefixCPUID) {
179 panic("CPUID memory space not yet implemented!\n");
180 } else if (prefix == IntAddrPrefixMSR) {
180 vaddr = vaddr >> 3;
181 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;
181 req->setFlags(Request::MMAPPED_IPR);
182 req->setFlags(Request::MMAPPED_IPR);
182 Addr regNum = 0;
183 switch (vaddr & ~IntAddrPrefixMask) {
184 case 0x10:
185 regNum = MISCREG_TSC;
186 break;
187 case 0x1B:
188 regNum = MISCREG_APIC_BASE;
189 break;
190 case 0xFE:
191 regNum = MISCREG_MTRRCAP;
192 break;
193 case 0x174:
194 regNum = MISCREG_SYSENTER_CS;
195 break;
196 case 0x175:
197 regNum = MISCREG_SYSENTER_ESP;
198 break;
199 case 0x176:
200 regNum = MISCREG_SYSENTER_EIP;
201 break;
202 case 0x179:
203 regNum = MISCREG_MCG_CAP;
204 break;
205 case 0x17A:
206 regNum = MISCREG_MCG_STATUS;
207 break;
208 case 0x17B:
209 regNum = MISCREG_MCG_CTL;
210 break;
211 case 0x1D9:
212 regNum = MISCREG_DEBUG_CTL_MSR;
213 break;
214 case 0x1DB:
215 regNum = MISCREG_LAST_BRANCH_FROM_IP;
216 break;
217 case 0x1DC:
218 regNum = MISCREG_LAST_BRANCH_TO_IP;
219 break;
220 case 0x1DD:
221 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
222 break;
223 case 0x1DE:
224 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
225 break;
226 case 0x200:
227 regNum = MISCREG_MTRR_PHYS_BASE_0;
228 break;
229 case 0x201:
230 regNum = MISCREG_MTRR_PHYS_MASK_0;
231 break;
232 case 0x202:
233 regNum = MISCREG_MTRR_PHYS_BASE_1;
234 break;
235 case 0x203:
236 regNum = MISCREG_MTRR_PHYS_MASK_1;
237 break;
238 case 0x204:
239 regNum = MISCREG_MTRR_PHYS_BASE_2;
240 break;
241 case 0x205:
242 regNum = MISCREG_MTRR_PHYS_MASK_2;
243 break;
244 case 0x206:
245 regNum = MISCREG_MTRR_PHYS_BASE_3;
246 break;
247 case 0x207:
248 regNum = MISCREG_MTRR_PHYS_MASK_3;
249 break;
250 case 0x208:
251 regNum = MISCREG_MTRR_PHYS_BASE_4;
252 break;
253 case 0x209:
254 regNum = MISCREG_MTRR_PHYS_MASK_4;
255 break;
256 case 0x20A:
257 regNum = MISCREG_MTRR_PHYS_BASE_5;
258 break;
259 case 0x20B:
260 regNum = MISCREG_MTRR_PHYS_MASK_5;
261 break;
262 case 0x20C:
263 regNum = MISCREG_MTRR_PHYS_BASE_6;
264 break;
265 case 0x20D:
266 regNum = MISCREG_MTRR_PHYS_MASK_6;
267 break;
268 case 0x20E:
269 regNum = MISCREG_MTRR_PHYS_BASE_7;
270 break;
271 case 0x20F:
272 regNum = MISCREG_MTRR_PHYS_MASK_7;
273 break;
274 case 0x250:
275 regNum = MISCREG_MTRR_FIX_64K_00000;
276 break;
277 case 0x258:
278 regNum = MISCREG_MTRR_FIX_16K_80000;
279 break;
280 case 0x259:
281 regNum = MISCREG_MTRR_FIX_16K_A0000;
282 break;
283 case 0x268:
284 regNum = MISCREG_MTRR_FIX_4K_C0000;
285 break;
286 case 0x269:
287 regNum = MISCREG_MTRR_FIX_4K_C8000;
288 break;
289 case 0x26A:
290 regNum = MISCREG_MTRR_FIX_4K_D0000;
291 break;
292 case 0x26B:
293 regNum = MISCREG_MTRR_FIX_4K_D8000;
294 break;
295 case 0x26C:
296 regNum = MISCREG_MTRR_FIX_4K_E0000;
297 break;
298 case 0x26D:
299 regNum = MISCREG_MTRR_FIX_4K_E8000;
300 break;
301 case 0x26E:
302 regNum = MISCREG_MTRR_FIX_4K_F0000;
303 break;
304 case 0x26F:
305 regNum = MISCREG_MTRR_FIX_4K_F8000;
306 break;
307 case 0x277:
308 regNum = MISCREG_PAT;
309 break;
310 case 0x2FF:
311 regNum = MISCREG_DEF_TYPE;
312 break;
313 case 0x400:
314 regNum = MISCREG_MC0_CTL;
315 break;
316 case 0x404:
317 regNum = MISCREG_MC1_CTL;
318 break;
319 case 0x408:
320 regNum = MISCREG_MC2_CTL;
321 break;
322 case 0x40C:
323 regNum = MISCREG_MC3_CTL;
324 break;
325 case 0x410:
326 regNum = MISCREG_MC4_CTL;
327 break;
328 case 0x414:
329 regNum = MISCREG_MC5_CTL;
330 break;
331 case 0x418:
332 regNum = MISCREG_MC6_CTL;
333 break;
334 case 0x41C:
335 regNum = MISCREG_MC7_CTL;
336 break;
337 case 0x401:
338 regNum = MISCREG_MC0_STATUS;
339 break;
340 case 0x405:
341 regNum = MISCREG_MC1_STATUS;
342 break;
343 case 0x409:
344 regNum = MISCREG_MC2_STATUS;
345 break;
346 case 0x40D:
347 regNum = MISCREG_MC3_STATUS;
348 break;
349 case 0x411:
350 regNum = MISCREG_MC4_STATUS;
351 break;
352 case 0x415:
353 regNum = MISCREG_MC5_STATUS;
354 break;
355 case 0x419:
356 regNum = MISCREG_MC6_STATUS;
357 break;
358 case 0x41D:
359 regNum = MISCREG_MC7_STATUS;
360 break;
361 case 0x402:
362 regNum = MISCREG_MC0_ADDR;
363 break;
364 case 0x406:
365 regNum = MISCREG_MC1_ADDR;
366 break;
367 case 0x40A:
368 regNum = MISCREG_MC2_ADDR;
369 break;
370 case 0x40E:
371 regNum = MISCREG_MC3_ADDR;
372 break;
373 case 0x412:
374 regNum = MISCREG_MC4_ADDR;
375 break;
376 case 0x416:
377 regNum = MISCREG_MC5_ADDR;
378 break;
379 case 0x41A:
380 regNum = MISCREG_MC6_ADDR;
381 break;
382 case 0x41E:
383 regNum = MISCREG_MC7_ADDR;
384 break;
385 case 0x403:
386 regNum = MISCREG_MC0_MISC;
387 break;
388 case 0x407:
389 regNum = MISCREG_MC1_MISC;
390 break;
391 case 0x40B:
392 regNum = MISCREG_MC2_MISC;
393 break;
394 case 0x40F:
395 regNum = MISCREG_MC3_MISC;
396 break;
397 case 0x413:
398 regNum = MISCREG_MC4_MISC;
399 break;
400 case 0x417:
401 regNum = MISCREG_MC5_MISC;
402 break;
403 case 0x41B:
404 regNum = MISCREG_MC6_MISC;
405 break;
406 case 0x41F:
407 regNum = MISCREG_MC7_MISC;
408 break;
409 case 0xC0000080:
410 regNum = MISCREG_EFER;
411 break;
412 case 0xC0000081:
413 regNum = MISCREG_STAR;
414 break;
415 case 0xC0000082:
416 regNum = MISCREG_LSTAR;
417 break;
418 case 0xC0000083:
419 regNum = MISCREG_CSTAR;
420 break;
421 case 0xC0000084:
422 regNum = MISCREG_SF_MASK;
423 break;
424 case 0xC0000100:
425 regNum = MISCREG_FS_BASE;
426 break;
427 case 0xC0000101:
428 regNum = MISCREG_GS_BASE;
429 break;
430 case 0xC0000102:
431 regNum = MISCREG_KERNEL_GS_BASE;
432 break;
433 case 0xC0000103:
434 regNum = MISCREG_TSC_AUX;
435 break;
436 case 0xC0010000:
437 regNum = MISCREG_PERF_EVT_SEL0;
438 break;
439 case 0xC0010001:
440 regNum = MISCREG_PERF_EVT_SEL1;
441 break;
442 case 0xC0010002:
443 regNum = MISCREG_PERF_EVT_SEL2;
444 break;
445 case 0xC0010003:
446 regNum = MISCREG_PERF_EVT_SEL3;
447 break;
448 case 0xC0010004:
449 regNum = MISCREG_PERF_EVT_CTR0;
450 break;
451 case 0xC0010005:
452 regNum = MISCREG_PERF_EVT_CTR1;
453 break;
454 case 0xC0010006:
455 regNum = MISCREG_PERF_EVT_CTR2;
456 break;
457 case 0xC0010007:
458 regNum = MISCREG_PERF_EVT_CTR3;
459 break;
460 case 0xC0010010:
461 regNum = MISCREG_SYSCFG;
462 break;
463 case 0xC0010016:
464 regNum = MISCREG_IORR_BASE0;
465 break;
466 case 0xC0010017:
467 regNum = MISCREG_IORR_BASE1;
468 break;
469 case 0xC0010018:
470 regNum = MISCREG_IORR_MASK0;
471 break;
472 case 0xC0010019:
473 regNum = MISCREG_IORR_MASK1;
474 break;
475 case 0xC001001A:
476 regNum = MISCREG_TOP_MEM;
477 break;
478 case 0xC001001D:
479 regNum = MISCREG_TOP_MEM2;
480 break;
481 case 0xC0010114:
482 regNum = MISCREG_VM_CR;
483 break;
484 case 0xC0010115:
485 regNum = MISCREG_IGNNE;
486 break;
487 case 0xC0010116:
488 regNum = MISCREG_SMM_CTL;
489 break;
490 case 0xC0010117:
491 regNum = MISCREG_VM_HSAVE_PA;
492 break;
493 default:
183
184 MiscRegIndex regNum;
185 if (!msrAddrToIndex(regNum, vaddr))
494 return new GeneralProtection(0);
186 return new GeneralProtection(0);
495 }
187
496 //The index is multiplied by the size of a MiscReg so that
497 //any memory dependence calculations will not see these as
498 //overlapping.
188 //The index is multiplied by the size of a MiscReg so that
189 //any memory dependence calculations will not see these as
190 //overlapping.
499 req->setPaddr(regNum * sizeof(MiscReg));
191 req->setPaddr((Addr)regNum * sizeof(MiscReg));
500 return NoFault;
501 } else if (prefix == IntAddrPrefixIO) {
502 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
503 // bitmap in the TSS.
504
505 Addr IOPort = vaddr & ~IntAddrPrefixMask;
506 // Make sure the address fits in the expected 16 bit IO address
507 // space.

--- 251 unchanged lines hidden --- 		192 return NoFault;
193 } else if (prefix == IntAddrPrefixIO) {
194 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
195 // bitmap in the TSS.
196
197 Addr IOPort = vaddr & ~IntAddrPrefixMask;
198 // Make sure the address fits in the expected 16 bit IO address
199 // space.

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