tlb.cc (6132:916f10213bea) tlb.cc (6141:5babc3f3d8c8)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

--- 172 unchanged lines hidden (view full) ---

181 EntryList::iterator entry = lookupIt(va, false);
182 if (entry != entryList.end()) {
183 freeList.push_back(*entry);
184 entryList.erase(entry);
185 }
186}
187
188Fault
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

--- 172 unchanged lines hidden (view full) ---

181 EntryList::iterator entry = lookupIt(va, false);
182 if (entry != entryList.end()) {
183 freeList.push_back(*entry);
184 entryList.erase(entry);
185 }
186}
187
188Fault
189TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
190 Mode mode, bool &delayedResponse, bool timing)
189TLB::translateInt(RequestPtr req, ThreadContext *tc)
191{
190{
192 delayedResponse = false;
191 DPRINTF(TLB, "Addresses references internal memory.\n");
193 Addr vaddr = req->getVaddr();
192 Addr vaddr = req->getVaddr();
194 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
195 uint32_t flags = req->getFlags();
196 bool storeCheck = flags & (StoreCheck << FlagShift);
193 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
194 if (prefix == IntAddrPrefixCPUID) {
195 panic("CPUID memory space not yet implemented!\n");
196 } else if (prefix == IntAddrPrefixMSR) {
197 vaddr = vaddr >> 3;
198 req->setMmapedIpr(true);
199 Addr regNum = 0;
200 switch (vaddr & ~IntAddrPrefixMask) {
201 case 0x10:
202 regNum = MISCREG_TSC;
203 break;
204 case 0x1B:
205 regNum = MISCREG_APIC_BASE;
206 break;
207 case 0xFE:
208 regNum = MISCREG_MTRRCAP;
209 break;
210 case 0x174:
211 regNum = MISCREG_SYSENTER_CS;
212 break;
213 case 0x175:
214 regNum = MISCREG_SYSENTER_ESP;
215 break;
216 case 0x176:
217 regNum = MISCREG_SYSENTER_EIP;
218 break;
219 case 0x179:
220 regNum = MISCREG_MCG_CAP;
221 break;
222 case 0x17A:
223 regNum = MISCREG_MCG_STATUS;
224 break;
225 case 0x17B:
226 regNum = MISCREG_MCG_CTL;
227 break;
228 case 0x1D9:
229 regNum = MISCREG_DEBUG_CTL_MSR;
230 break;
231 case 0x1DB:
232 regNum = MISCREG_LAST_BRANCH_FROM_IP;
233 break;
234 case 0x1DC:
235 regNum = MISCREG_LAST_BRANCH_TO_IP;
236 break;
237 case 0x1DD:
238 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
239 break;
240 case 0x1DE:
241 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
242 break;
243 case 0x200:
244 regNum = MISCREG_MTRR_PHYS_BASE_0;
245 break;
246 case 0x201:
247 regNum = MISCREG_MTRR_PHYS_MASK_0;
248 break;
249 case 0x202:
250 regNum = MISCREG_MTRR_PHYS_BASE_1;
251 break;
252 case 0x203:
253 regNum = MISCREG_MTRR_PHYS_MASK_1;
254 break;
255 case 0x204:
256 regNum = MISCREG_MTRR_PHYS_BASE_2;
257 break;
258 case 0x205:
259 regNum = MISCREG_MTRR_PHYS_MASK_2;
260 break;
261 case 0x206:
262 regNum = MISCREG_MTRR_PHYS_BASE_3;
263 break;
264 case 0x207:
265 regNum = MISCREG_MTRR_PHYS_MASK_3;
266 break;
267 case 0x208:
268 regNum = MISCREG_MTRR_PHYS_BASE_4;
269 break;
270 case 0x209:
271 regNum = MISCREG_MTRR_PHYS_MASK_4;
272 break;
273 case 0x20A:
274 regNum = MISCREG_MTRR_PHYS_BASE_5;
275 break;
276 case 0x20B:
277 regNum = MISCREG_MTRR_PHYS_MASK_5;
278 break;
279 case 0x20C:
280 regNum = MISCREG_MTRR_PHYS_BASE_6;
281 break;
282 case 0x20D:
283 regNum = MISCREG_MTRR_PHYS_MASK_6;
284 break;
285 case 0x20E:
286 regNum = MISCREG_MTRR_PHYS_BASE_7;
287 break;
288 case 0x20F:
289 regNum = MISCREG_MTRR_PHYS_MASK_7;
290 break;
291 case 0x250:
292 regNum = MISCREG_MTRR_FIX_64K_00000;
293 break;
294 case 0x258:
295 regNum = MISCREG_MTRR_FIX_16K_80000;
296 break;
297 case 0x259:
298 regNum = MISCREG_MTRR_FIX_16K_A0000;
299 break;
300 case 0x268:
301 regNum = MISCREG_MTRR_FIX_4K_C0000;
302 break;
303 case 0x269:
304 regNum = MISCREG_MTRR_FIX_4K_C8000;
305 break;
306 case 0x26A:
307 regNum = MISCREG_MTRR_FIX_4K_D0000;
308 break;
309 case 0x26B:
310 regNum = MISCREG_MTRR_FIX_4K_D8000;
311 break;
312 case 0x26C:
313 regNum = MISCREG_MTRR_FIX_4K_E0000;
314 break;
315 case 0x26D:
316 regNum = MISCREG_MTRR_FIX_4K_E8000;
317 break;
318 case 0x26E:
319 regNum = MISCREG_MTRR_FIX_4K_F0000;
320 break;
321 case 0x26F:
322 regNum = MISCREG_MTRR_FIX_4K_F8000;
323 break;
324 case 0x277:
325 regNum = MISCREG_PAT;
326 break;
327 case 0x2FF:
328 regNum = MISCREG_DEF_TYPE;
329 break;
330 case 0x400:
331 regNum = MISCREG_MC0_CTL;
332 break;
333 case 0x404:
334 regNum = MISCREG_MC1_CTL;
335 break;
336 case 0x408:
337 regNum = MISCREG_MC2_CTL;
338 break;
339 case 0x40C:
340 regNum = MISCREG_MC3_CTL;
341 break;
342 case 0x410:
343 regNum = MISCREG_MC4_CTL;
344 break;
345 case 0x414:
346 regNum = MISCREG_MC5_CTL;
347 break;
348 case 0x418:
349 regNum = MISCREG_MC6_CTL;
350 break;
351 case 0x41C:
352 regNum = MISCREG_MC7_CTL;
353 break;
354 case 0x401:
355 regNum = MISCREG_MC0_STATUS;
356 break;
357 case 0x405:
358 regNum = MISCREG_MC1_STATUS;
359 break;
360 case 0x409:
361 regNum = MISCREG_MC2_STATUS;
362 break;
363 case 0x40D:
364 regNum = MISCREG_MC3_STATUS;
365 break;
366 case 0x411:
367 regNum = MISCREG_MC4_STATUS;
368 break;
369 case 0x415:
370 regNum = MISCREG_MC5_STATUS;
371 break;
372 case 0x419:
373 regNum = MISCREG_MC6_STATUS;
374 break;
375 case 0x41D:
376 regNum = MISCREG_MC7_STATUS;
377 break;
378 case 0x402:
379 regNum = MISCREG_MC0_ADDR;
380 break;
381 case 0x406:
382 regNum = MISCREG_MC1_ADDR;
383 break;
384 case 0x40A:
385 regNum = MISCREG_MC2_ADDR;
386 break;
387 case 0x40E:
388 regNum = MISCREG_MC3_ADDR;
389 break;
390 case 0x412:
391 regNum = MISCREG_MC4_ADDR;
392 break;
393 case 0x416:
394 regNum = MISCREG_MC5_ADDR;
395 break;
396 case 0x41A:
397 regNum = MISCREG_MC6_ADDR;
398 break;
399 case 0x41E:
400 regNum = MISCREG_MC7_ADDR;
401 break;
402 case 0x403:
403 regNum = MISCREG_MC0_MISC;
404 break;
405 case 0x407:
406 regNum = MISCREG_MC1_MISC;
407 break;
408 case 0x40B:
409 regNum = MISCREG_MC2_MISC;
410 break;
411 case 0x40F:
412 regNum = MISCREG_MC3_MISC;
413 break;
414 case 0x413:
415 regNum = MISCREG_MC4_MISC;
416 break;
417 case 0x417:
418 regNum = MISCREG_MC5_MISC;
419 break;
420 case 0x41B:
421 regNum = MISCREG_MC6_MISC;
422 break;
423 case 0x41F:
424 regNum = MISCREG_MC7_MISC;
425 break;
426 case 0xC0000080:
427 regNum = MISCREG_EFER;
428 break;
429 case 0xC0000081:
430 regNum = MISCREG_STAR;
431 break;
432 case 0xC0000082:
433 regNum = MISCREG_LSTAR;
434 break;
435 case 0xC0000083:
436 regNum = MISCREG_CSTAR;
437 break;
438 case 0xC0000084:
439 regNum = MISCREG_SF_MASK;
440 break;
441 case 0xC0000100:
442 regNum = MISCREG_FS_BASE;
443 break;
444 case 0xC0000101:
445 regNum = MISCREG_GS_BASE;
446 break;
447 case 0xC0000102:
448 regNum = MISCREG_KERNEL_GS_BASE;
449 break;
450 case 0xC0000103:
451 regNum = MISCREG_TSC_AUX;
452 break;
453 case 0xC0010000:
454 regNum = MISCREG_PERF_EVT_SEL0;
455 break;
456 case 0xC0010001:
457 regNum = MISCREG_PERF_EVT_SEL1;
458 break;
459 case 0xC0010002:
460 regNum = MISCREG_PERF_EVT_SEL2;
461 break;
462 case 0xC0010003:
463 regNum = MISCREG_PERF_EVT_SEL3;
464 break;
465 case 0xC0010004:
466 regNum = MISCREG_PERF_EVT_CTR0;
467 break;
468 case 0xC0010005:
469 regNum = MISCREG_PERF_EVT_CTR1;
470 break;
471 case 0xC0010006:
472 regNum = MISCREG_PERF_EVT_CTR2;
473 break;
474 case 0xC0010007:
475 regNum = MISCREG_PERF_EVT_CTR3;
476 break;
477 case 0xC0010010:
478 regNum = MISCREG_SYSCFG;
479 break;
480 case 0xC0010016:
481 regNum = MISCREG_IORR_BASE0;
482 break;
483 case 0xC0010017:
484 regNum = MISCREG_IORR_BASE1;
485 break;
486 case 0xC0010018:
487 regNum = MISCREG_IORR_MASK0;
488 break;
489 case 0xC0010019:
490 regNum = MISCREG_IORR_MASK1;
491 break;
492 case 0xC001001A:
493 regNum = MISCREG_TOP_MEM;
494 break;
495 case 0xC001001D:
496 regNum = MISCREG_TOP_MEM2;
497 break;
498 case 0xC0010114:
499 regNum = MISCREG_VM_CR;
500 break;
501 case 0xC0010115:
502 regNum = MISCREG_IGNNE;
503 break;
504 case 0xC0010116:
505 regNum = MISCREG_SMM_CTL;
506 break;
507 case 0xC0010117:
508 regNum = MISCREG_VM_HSAVE_PA;
509 break;
510 default:
511 return new GeneralProtection(0);
512 }
513 //The index is multiplied by the size of a MiscReg so that
514 //any memory dependence calculations will not see these as
515 //overlapping.
516 req->setPaddr(regNum * sizeof(MiscReg));
517 return NoFault;
518 } else if (prefix == IntAddrPrefixIO) {
519 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
520 // bitmap in the TSS.
197
521
198 int seg = flags & SegmentFlagMask;
199
200 // If this is true, we're dealing with a request to read an internal
201 // value.
202 if (seg == SEGMENT_REG_MS) {
203 DPRINTF(TLB, "Addresses references internal memory.\n");
204 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
205 if (prefix == IntAddrPrefixCPUID) {
206 panic("CPUID memory space not yet implemented!\n");
207 } else if (prefix == IntAddrPrefixMSR) {
208 vaddr = vaddr >> 3;
522 Addr IOPort = vaddr & ~IntAddrPrefixMask;
523 // Make sure the address fits in the expected 16 bit IO address
524 // space.
525 assert(!(IOPort & ~0xFFFF));
526 if (IOPort == 0xCF8 && req->getSize() == 4) {
209 req->setMmapedIpr(true);
527 req->setMmapedIpr(true);
210 Addr regNum = 0;
211 switch (vaddr & ~IntAddrPrefixMask) {
212 case 0x10:
213 regNum = MISCREG_TSC;
214 break;
215 case 0x1B:
216 regNum = MISCREG_APIC_BASE;
217 break;
218 case 0xFE:
219 regNum = MISCREG_MTRRCAP;
220 break;
221 case 0x174:
222 regNum = MISCREG_SYSENTER_CS;
223 break;
224 case 0x175:
225 regNum = MISCREG_SYSENTER_ESP;
226 break;
227 case 0x176:
228 regNum = MISCREG_SYSENTER_EIP;
229 break;
230 case 0x179:
231 regNum = MISCREG_MCG_CAP;
232 break;
233 case 0x17A:
234 regNum = MISCREG_MCG_STATUS;
235 break;
236 case 0x17B:
237 regNum = MISCREG_MCG_CTL;
238 break;
239 case 0x1D9:
240 regNum = MISCREG_DEBUG_CTL_MSR;
241 break;
242 case 0x1DB:
243 regNum = MISCREG_LAST_BRANCH_FROM_IP;
244 break;
245 case 0x1DC:
246 regNum = MISCREG_LAST_BRANCH_TO_IP;
247 break;
248 case 0x1DD:
249 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
250 break;
251 case 0x1DE:
252 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
253 break;
254 case 0x200:
255 regNum = MISCREG_MTRR_PHYS_BASE_0;
256 break;
257 case 0x201:
258 regNum = MISCREG_MTRR_PHYS_MASK_0;
259 break;
260 case 0x202:
261 regNum = MISCREG_MTRR_PHYS_BASE_1;
262 break;
263 case 0x203:
264 regNum = MISCREG_MTRR_PHYS_MASK_1;
265 break;
266 case 0x204:
267 regNum = MISCREG_MTRR_PHYS_BASE_2;
268 break;
269 case 0x205:
270 regNum = MISCREG_MTRR_PHYS_MASK_2;
271 break;
272 case 0x206:
273 regNum = MISCREG_MTRR_PHYS_BASE_3;
274 break;
275 case 0x207:
276 regNum = MISCREG_MTRR_PHYS_MASK_3;
277 break;
278 case 0x208:
279 regNum = MISCREG_MTRR_PHYS_BASE_4;
280 break;
281 case 0x209:
282 regNum = MISCREG_MTRR_PHYS_MASK_4;
283 break;
284 case 0x20A:
285 regNum = MISCREG_MTRR_PHYS_BASE_5;
286 break;
287 case 0x20B:
288 regNum = MISCREG_MTRR_PHYS_MASK_5;
289 break;
290 case 0x20C:
291 regNum = MISCREG_MTRR_PHYS_BASE_6;
292 break;
293 case 0x20D:
294 regNum = MISCREG_MTRR_PHYS_MASK_6;
295 break;
296 case 0x20E:
297 regNum = MISCREG_MTRR_PHYS_BASE_7;
298 break;
299 case 0x20F:
300 regNum = MISCREG_MTRR_PHYS_MASK_7;
301 break;
302 case 0x250:
303 regNum = MISCREG_MTRR_FIX_64K_00000;
304 break;
305 case 0x258:
306 regNum = MISCREG_MTRR_FIX_16K_80000;
307 break;
308 case 0x259:
309 regNum = MISCREG_MTRR_FIX_16K_A0000;
310 break;
311 case 0x268:
312 regNum = MISCREG_MTRR_FIX_4K_C0000;
313 break;
314 case 0x269:
315 regNum = MISCREG_MTRR_FIX_4K_C8000;
316 break;
317 case 0x26A:
318 regNum = MISCREG_MTRR_FIX_4K_D0000;
319 break;
320 case 0x26B:
321 regNum = MISCREG_MTRR_FIX_4K_D8000;
322 break;
323 case 0x26C:
324 regNum = MISCREG_MTRR_FIX_4K_E0000;
325 break;
326 case 0x26D:
327 regNum = MISCREG_MTRR_FIX_4K_E8000;
328 break;
329 case 0x26E:
330 regNum = MISCREG_MTRR_FIX_4K_F0000;
331 break;
332 case 0x26F:
333 regNum = MISCREG_MTRR_FIX_4K_F8000;
334 break;
335 case 0x277:
336 regNum = MISCREG_PAT;
337 break;
338 case 0x2FF:
339 regNum = MISCREG_DEF_TYPE;
340 break;
341 case 0x400:
342 regNum = MISCREG_MC0_CTL;
343 break;
344 case 0x404:
345 regNum = MISCREG_MC1_CTL;
346 break;
347 case 0x408:
348 regNum = MISCREG_MC2_CTL;
349 break;
350 case 0x40C:
351 regNum = MISCREG_MC3_CTL;
352 break;
353 case 0x410:
354 regNum = MISCREG_MC4_CTL;
355 break;
356 case 0x414:
357 regNum = MISCREG_MC5_CTL;
358 break;
359 case 0x418:
360 regNum = MISCREG_MC6_CTL;
361 break;
362 case 0x41C:
363 regNum = MISCREG_MC7_CTL;
364 break;
365 case 0x401:
366 regNum = MISCREG_MC0_STATUS;
367 break;
368 case 0x405:
369 regNum = MISCREG_MC1_STATUS;
370 break;
371 case 0x409:
372 regNum = MISCREG_MC2_STATUS;
373 break;
374 case 0x40D:
375 regNum = MISCREG_MC3_STATUS;
376 break;
377 case 0x411:
378 regNum = MISCREG_MC4_STATUS;
379 break;
380 case 0x415:
381 regNum = MISCREG_MC5_STATUS;
382 break;
383 case 0x419:
384 regNum = MISCREG_MC6_STATUS;
385 break;
386 case 0x41D:
387 regNum = MISCREG_MC7_STATUS;
388 break;
389 case 0x402:
390 regNum = MISCREG_MC0_ADDR;
391 break;
392 case 0x406:
393 regNum = MISCREG_MC1_ADDR;
394 break;
395 case 0x40A:
396 regNum = MISCREG_MC2_ADDR;
397 break;
398 case 0x40E:
399 regNum = MISCREG_MC3_ADDR;
400 break;
401 case 0x412:
402 regNum = MISCREG_MC4_ADDR;
403 break;
404 case 0x416:
405 regNum = MISCREG_MC5_ADDR;
406 break;
407 case 0x41A:
408 regNum = MISCREG_MC6_ADDR;
409 break;
410 case 0x41E:
411 regNum = MISCREG_MC7_ADDR;
412 break;
413 case 0x403:
414 regNum = MISCREG_MC0_MISC;
415 break;
416 case 0x407:
417 regNum = MISCREG_MC1_MISC;
418 break;
419 case 0x40B:
420 regNum = MISCREG_MC2_MISC;
421 break;
422 case 0x40F:
423 regNum = MISCREG_MC3_MISC;
424 break;
425 case 0x413:
426 regNum = MISCREG_MC4_MISC;
427 break;
428 case 0x417:
429 regNum = MISCREG_MC5_MISC;
430 break;
431 case 0x41B:
432 regNum = MISCREG_MC6_MISC;
433 break;
434 case 0x41F:
435 regNum = MISCREG_MC7_MISC;
436 break;
437 case 0xC0000080:
438 regNum = MISCREG_EFER;
439 break;
440 case 0xC0000081:
441 regNum = MISCREG_STAR;
442 break;
443 case 0xC0000082:
444 regNum = MISCREG_LSTAR;
445 break;
446 case 0xC0000083:
447 regNum = MISCREG_CSTAR;
448 break;
449 case 0xC0000084:
450 regNum = MISCREG_SF_MASK;
451 break;
452 case 0xC0000100:
453 regNum = MISCREG_FS_BASE;
454 break;
455 case 0xC0000101:
456 regNum = MISCREG_GS_BASE;
457 break;
458 case 0xC0000102:
459 regNum = MISCREG_KERNEL_GS_BASE;
460 break;
461 case 0xC0000103:
462 regNum = MISCREG_TSC_AUX;
463 break;
464 case 0xC0010000:
465 regNum = MISCREG_PERF_EVT_SEL0;
466 break;
467 case 0xC0010001:
468 regNum = MISCREG_PERF_EVT_SEL1;
469 break;
470 case 0xC0010002:
471 regNum = MISCREG_PERF_EVT_SEL2;
472 break;
473 case 0xC0010003:
474 regNum = MISCREG_PERF_EVT_SEL3;
475 break;
476 case 0xC0010004:
477 regNum = MISCREG_PERF_EVT_CTR0;
478 break;
479 case 0xC0010005:
480 regNum = MISCREG_PERF_EVT_CTR1;
481 break;
482 case 0xC0010006:
483 regNum = MISCREG_PERF_EVT_CTR2;
484 break;
485 case 0xC0010007:
486 regNum = MISCREG_PERF_EVT_CTR3;
487 break;
488 case 0xC0010010:
489 regNum = MISCREG_SYSCFG;
490 break;
491 case 0xC0010016:
492 regNum = MISCREG_IORR_BASE0;
493 break;
494 case 0xC0010017:
495 regNum = MISCREG_IORR_BASE1;
496 break;
497 case 0xC0010018:
498 regNum = MISCREG_IORR_MASK0;
499 break;
500 case 0xC0010019:
501 regNum = MISCREG_IORR_MASK1;
502 break;
503 case 0xC001001A:
504 regNum = MISCREG_TOP_MEM;
505 break;
506 case 0xC001001D:
507 regNum = MISCREG_TOP_MEM2;
508 break;
509 case 0xC0010114:
510 regNum = MISCREG_VM_CR;
511 break;
512 case 0xC0010115:
513 regNum = MISCREG_IGNNE;
514 break;
515 case 0xC0010116:
516 regNum = MISCREG_SMM_CTL;
517 break;
518 case 0xC0010117:
519 regNum = MISCREG_VM_HSAVE_PA;
520 break;
521 default:
522 return new GeneralProtection(0);
528 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
529 } else if ((IOPort & ~mask(2)) == 0xCFC) {
530 Addr configAddress =
531 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
532 if (bits(configAddress, 31, 31)) {
533 req->setPaddr(PhysAddrPrefixPciConfig |
534 mbits(configAddress, 30, 2) |
535 (IOPort & mask(2)));
523 }
536 }
524 //The index is multiplied by the size of a MiscReg so that
525 //any memory dependence calculations will not see these as
526 //overlapping.
527 req->setPaddr(regNum * sizeof(MiscReg));
528 return NoFault;
529 } else if (prefix == IntAddrPrefixIO) {
530 // TODO If CPL > IOPL or in virtual mode, check the I/O permission
531 // bitmap in the TSS.
532
533 Addr IOPort = vaddr & ~IntAddrPrefixMask;
534 // Make sure the address fits in the expected 16 bit IO address
535 // space.
536 assert(!(IOPort & ~0xFFFF));
537 if (IOPort == 0xCF8 && req->getSize() == 4) {
538 req->setMmapedIpr(true);
539 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg));
540 } else if ((IOPort & ~mask(2)) == 0xCFC) {
541 Addr configAddress =
542 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS);
543 if (bits(configAddress, 31, 31)) {
544 req->setPaddr(PhysAddrPrefixPciConfig |
545 mbits(configAddress, 30, 2) |
546 (IOPort & mask(2)));
547 }
548 } else {
549 req->setPaddr(PhysAddrPrefixIO | IOPort);
550 }
551 return NoFault;
552 } else {
537 } else {
553 panic("Access to unrecognized internal address space %#x.\n",
554 prefix);
538 req->setPaddr(PhysAddrPrefixIO | IOPort);
555 }
539 }
540 return NoFault;
541 } else {
542 panic("Access to unrecognized internal address space %#x.\n",
543 prefix);
556 }
544 }
545}
557
546
558 // Get cr0. This will tell us how to do translation. We'll assume it was
559 // verified to be correct and consistent when set.
560 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
547Fault
548TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
549 Mode mode, bool &delayedResponse, bool timing)
550{
551 uint32_t flags = req->getFlags();
552 int seg = flags & SegmentFlagMask;
553 bool storeCheck = flags & (StoreCheck << FlagShift);
561
554
555 // If this is true, we're dealing with a request to a non-memory address
556 // space.
557 if (seg == SEGMENT_REG_MS) {
558 return translateInt(req, tc);
559 }
560
561 delayedResponse = false;
562 Addr vaddr = req->getVaddr();
563 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
564
565 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
566
562 // If protected mode has been enabled...
567 // If protected mode has been enabled...
563 if (cr0.pe) {
568 if (m5Reg.prot) {
564 DPRINTF(TLB, "In protected mode.\n");
569 DPRINTF(TLB, "In protected mode.\n");
565 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
566 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
567 // If we're not in 64-bit mode, do protection/limit checks
570 // If we're not in 64-bit mode, do protection/limit checks
568 if (!efer.lma || !csAttr.longMode) {
571 if (m5Reg.mode != LongMode) {
569 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
570 // Check for a NULL segment selector.
571 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
572 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
573 // Check for a NULL segment selector.
574 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
572 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS ||
573 seg == SEGMENT_REG_MS)
575 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS)
574 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
575 return new GeneralProtection(0);
576 bool expandDown = false;
577 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
578 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
579 if (!attr.writable && (mode == Write || storeCheck))
580 return new GeneralProtection(0);
581 if (!attr.readable && mode == Read)
582 return new GeneralProtection(0);
583 expandDown = attr.expandDown;
584
585 }
586 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
587 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
588 // This assumes we're not in 64 bit mode. If we were, the default
589 // address size is 64 bits, overridable to 32.
590 int size = 32;
591 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
576 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
577 return new GeneralProtection(0);
578 bool expandDown = false;
579 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
580 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
581 if (!attr.writable && (mode == Write || storeCheck))
582 return new GeneralProtection(0);
583 if (!attr.readable && mode == Read)
584 return new GeneralProtection(0);
585 expandDown = attr.expandDown;
586
587 }
588 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
589 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
590 // This assumes we're not in 64 bit mode. If we were, the default
591 // address size is 64 bits, overridable to 32.
592 int size = 32;
593 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift));
594 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
592 if ((csAttr.defaultSize && sizeOverride) ||
593 (!csAttr.defaultSize && !sizeOverride))
594 size = 16;
595 Addr offset = bits(vaddr - base, size-1, 0);
596 Addr endOffset = offset + req->getSize() - 1;
597 if (expandDown) {
598 DPRINTF(TLB, "Checking an expand down segment.\n");
599 warn_once("Expand down segments are untested.\n");
600 if (offset <= limit || endOffset <= limit)
601 return new GeneralProtection(0);
602 } else {
603 if (offset > limit || endOffset > limit)
604 return new GeneralProtection(0);
605 }
606 }
607 // If paging is enabled, do the translation.
595 if ((csAttr.defaultSize && sizeOverride) ||
596 (!csAttr.defaultSize && !sizeOverride))
597 size = 16;
598 Addr offset = bits(vaddr - base, size-1, 0);
599 Addr endOffset = offset + req->getSize() - 1;
600 if (expandDown) {
601 DPRINTF(TLB, "Checking an expand down segment.\n");
602 warn_once("Expand down segments are untested.\n");
603 if (offset <= limit || endOffset <= limit)
604 return new GeneralProtection(0);
605 } else {
606 if (offset > limit || endOffset > limit)
607 return new GeneralProtection(0);
608 }
609 }
610 // If paging is enabled, do the translation.
608 if (cr0.pg) {
611 if (m5Reg.paging) {
609 DPRINTF(TLB, "Paging enabled.\n");
610 // The vaddr already has the segment base applied.
611 TlbEntry *entry = lookup(vaddr);
612 if (!entry) {
613#if FULL_SYSTEM
614 Fault fault = walker->start(tc, translation, req, mode);
615 if (timing || fault != NoFault) {
616 // This gets ignored in atomic mode.

--- 21 unchanged lines hidden (view full) ---

638 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
639 newEntry.pageStart());
640 entry = insert(alignedVaddr, newEntry);
641 }
642 DPRINTF(TLB, "Miss was serviced.\n");
643#endif
644 }
645 // Do paging protection checks.
612 DPRINTF(TLB, "Paging enabled.\n");
613 // The vaddr already has the segment base applied.
614 TlbEntry *entry = lookup(vaddr);
615 if (!entry) {
616#if FULL_SYSTEM
617 Fault fault = walker->start(tc, translation, req, mode);
618 if (timing || fault != NoFault) {
619 // This gets ignored in atomic mode.

--- 21 unchanged lines hidden (view full) ---

641 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr,
642 newEntry.pageStart());
643 entry = insert(alignedVaddr, newEntry);
644 }
645 DPRINTF(TLB, "Miss was serviced.\n");
646#endif
647 }
648 // Do paging protection checks.
646 bool inUser = (csAttr.dpl == 3 &&
649 bool inUser = (m5Reg.cpl == 3 &&
647 !(flags & (CPL0FlagBit << FlagShift)));
648 if ((inUser && !entry->user) ||
649 (mode == Write && !entry->writable)) {
650 // The page must have been present to get into the TLB in
651 // the first place. We'll assume the reserved bits are
652 // fine even though we're not checking them.
653 return new PageFault(vaddr, true, mode, inUser, false);
654 }

--- 101 unchanged lines hidden --- 		650 !(flags & (CPL0FlagBit << FlagShift)));
651 if ((inUser && !entry->user) ||
652 (mode == Write && !entry->writable)) {
653 // The page must have been present to get into the TLB in
654 // the first place. We'll assume the reserved bits are
655 // fine even though we're not checking them.
656 return new PageFault(vaddr, true, mode, inUser, false);
657 }

--- 101 unchanged lines hidden ---