tlb.cc (6059:d78df8ebc225) tlb.cc (6099:74e5e063a03d)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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192 delayedResponse = false;
193 Addr vaddr = req->getVaddr();
194 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
195 uint32_t flags = req->getFlags();
196 bool storeCheck = flags & StoreCheck;
197
198 int seg = flags & SegmentFlagMask;
199
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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192 delayedResponse = false;
193 Addr vaddr = req->getVaddr();
194 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
195 uint32_t flags = req->getFlags();
196 bool storeCheck = flags & StoreCheck;
197
198 int seg = flags & SegmentFlagMask;
199
200 //XXX Junk code to surpress the warning
201 if (storeCheck);
202
203 // If this is true, we're dealing with a request to read an internal
204 // value.
205 if (seg == SEGMENT_REG_MS) {
206 DPRINTF(TLB, "Addresses references internal memory.\n");
207 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
208 if (prefix == IntAddrPrefixCPUID) {
209 panic("CPUID memory space not yet implemented!\n");
210 } else if (prefix == IntAddrPrefixMSR) {

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574 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
575 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS ||
576 seg == SEGMENT_REG_MS)
577 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
578 return new GeneralProtection(0);
579 bool expandDown = false;
580 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
581 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
200 // If this is true, we're dealing with a request to read an internal
201 // value.
202 if (seg == SEGMENT_REG_MS) {
203 DPRINTF(TLB, "Addresses references internal memory.\n");
204 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
205 if (prefix == IntAddrPrefixCPUID) {
206 panic("CPUID memory space not yet implemented!\n");
207 } else if (prefix == IntAddrPrefixMSR) {

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571 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR ||
572 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS ||
573 seg == SEGMENT_REG_MS)
574 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg)))
575 return new GeneralProtection(0);
576 bool expandDown = false;
577 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
578 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) {
582 if (!attr.writable && mode == Write)
579 if (!attr.writable && (mode == Write || storeCheck))
583 return new GeneralProtection(0);
584 if (!attr.readable && mode == Read)
585 return new GeneralProtection(0);
586 expandDown = attr.expandDown;
587
588 }
589 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
590 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));

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650 !(flags & (CPL0FlagBit << FlagShift)));
651 if ((inUser && !entry->user) ||
652 (mode == Write && !entry->writable)) {
653 // The page must have been present to get into the TLB in
654 // the first place. We'll assume the reserved bits are
655 // fine even though we're not checking them.
656 return new PageFault(vaddr, true, mode, inUser, false);
657 }
580 return new GeneralProtection(0);
581 if (!attr.readable && mode == Read)
582 return new GeneralProtection(0);
583 expandDown = attr.expandDown;
584
585 }
586 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
587 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));

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647 !(flags & (CPL0FlagBit << FlagShift)));
648 if ((inUser && !entry->user) ||
649 (mode == Write && !entry->writable)) {
650 // The page must have been present to get into the TLB in
651 // the first place. We'll assume the reserved bits are
652 // fine even though we're not checking them.
653 return new PageFault(vaddr, true, mode, inUser, false);
654 }
655 if (storeCheck && !entry->writable) {
656 // This would fault if this were a write, so return a page
657 // fault that reflects that happening.
658 return new PageFault(vaddr, true, Write, inUser, false);
659 }
658
659
660 DPRINTF(TLB, "Entry found with paddr %#x, "
661 "doing protection checks.\n", entry->paddr);
662 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
663 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
664 req->setPaddr(paddr);
665 } else {

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661
662 DPRINTF(TLB, "Entry found with paddr %#x, "
663 "doing protection checks.\n", entry->paddr);
664 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
665 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
666 req->setPaddr(paddr);
667 } else {

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