tlb.cc (5980:0ea37baabfb0) tlb.cc (6022:410194bb3049)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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695 req->setFlags(Request::UNCACHEABLE);
696 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
697 }
698#endif
699 return NoFault;
700};
701
702Fault
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

--- 686 unchanged lines hidden (view full) ---

695 req->setFlags(Request::UNCACHEABLE);
696 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
697 }
698#endif
699 return NoFault;
700};
701
702Fault
703DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
703TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
704 bool write, bool execute)
704{
705 bool delayedResponse;
706 return TLB::translate(req, tc, NULL, write,
705{
706 bool delayedResponse;
707 return TLB::translate(req, tc, NULL, write,
707 false, delayedResponse, false);
708 execute, delayedResponse, false);
708}
709
710void
709}
710
711void
711DTB::translateTiming(RequestPtr req, ThreadContext *tc,
712 Translation *translation, bool write)
712TLB::translateTiming(RequestPtr req, ThreadContext *tc,
713 Translation *translation, bool write, bool execute)
713{
714 bool delayedResponse;
715 assert(translation);
716 Fault fault = TLB::translate(req, tc, translation,
714{
715 bool delayedResponse;
716 assert(translation);
717 Fault fault = TLB::translate(req, tc, translation,
717 write, false, delayedResponse, true);
718 write, execute, delayedResponse, true);
718 if (!delayedResponse)
719 if (!delayedResponse)
719 translation->finish(fault, req, tc, write);
720 translation->finish(fault, req, tc, write, execute);
720}
721
721}
722
722Fault
723ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
724{
725 bool delayedResponse;
726 return TLB::translate(req, tc, NULL, false,
727 true, delayedResponse, false);
728}
729
730void
731ITB::translateTiming(RequestPtr req, ThreadContext *tc,
732 Translation *translation)
733{
734 bool delayedResponse;
735 assert(translation);
736 Fault fault = TLB::translate(req, tc, translation,
737 false, true, delayedResponse, true);
738 if (!delayedResponse)
739 translation->finish(fault, req, tc, false);
740}
741
742#if FULL_SYSTEM
743
744Tick
723#if FULL_SYSTEM
724
725Tick
745DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
726TLB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
746{
747 return tc->getCpuPtr()->ticks(1);
748}
749
750Tick
727{
728 return tc->getCpuPtr()->ticks(1);
729}
730
731Tick
751DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
732TLB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
752{
753 return tc->getCpuPtr()->ticks(1);
754}
755
756#endif
757
758void
759TLB::serialize(std::ostream &os)
760{
761}
762
763void
764TLB::unserialize(Checkpoint *cp, const std::string &section)
765{
766}
767
733{
734 return tc->getCpuPtr()->ticks(1);
735}
736
737#endif
738
739void
740TLB::serialize(std::ostream &os)
741{
742}
743
744void
745TLB::unserialize(Checkpoint *cp, const std::string &section)
746{
747}
748
768void
769DTB::serialize(std::ostream &os)
770{
771 TLB::serialize(os);
772}
773
774void
775DTB::unserialize(Checkpoint *cp, const std::string &section)
776{
777 TLB::unserialize(cp, section);
778}
779
780/* end namespace X86ISA */ }
781
749/* end namespace X86ISA */ }
750
782X86ISA::ITB *
783X86ITBParams::create()
751X86ISA::TLB *
752X86TLBParams::create()
784{
753{
785 return new X86ISA::ITB(this);
754 return new X86ISA::TLB(this);
786}
755}
787
788X86ISA::DTB *
789X86DTBParams::create()
790{
791 return new X86ISA::DTB(this);
792}