tlb.cc (5891:73084c6bb183) tlb.cc (5894:8091ac99341a)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
193TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
193TLB::translateAtomic(RequestPtr req, ThreadContext *tc,
194 bool write, bool execute)
195{
196 Addr vaddr = req->getVaddr();
197 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
198 uint32_t flags = req->getFlags();
199 bool storeCheck = flags & StoreCheck;
200
201 int seg = flags & mask(4);

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658 req->setFlags(Request::UNCACHEABLE);
659 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
660 }
661#endif
662 return NoFault;
663};
664
665Fault
194 bool write, bool execute)
195{
196 Addr vaddr = req->getVaddr();
197 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
198 uint32_t flags = req->getFlags();
199 bool storeCheck = flags & StoreCheck;
200
201 int seg = flags & mask(4);

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658 req->setFlags(Request::UNCACHEABLE);
659 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
660 }
661#endif
662 return NoFault;
663};
664
665Fault
666DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
666DTB::translateAtomic(RequestPtr req, ThreadContext *tc, bool write)
667{
668 return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
669}
670
667{
668 return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
669}
670
671void
672DTB::translateTiming(RequestPtr req, ThreadContext *tc,
673 Translation *translation, bool write)
674{
675 assert(translation);
676 translation->finish(translateAtomic(req, tc, write), req, tc, write);
677}
678
671Fault
679Fault
672ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
680ITB::translateAtomic(RequestPtr req, ThreadContext *tc)
673{
674 return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
675}
676
681{
682 return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
683}
684
685void
686ITB::translateTiming(RequestPtr req, ThreadContext *tc,
687 Translation *translation)
688{
689 assert(translation);
690 translation->finish(translateAtomic(req, tc), req, tc, false);
691}
692
677#if FULL_SYSTEM
678
679Tick
680DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
681{
682 return tc->getCpuPtr()->ticks(1);
683}
684

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694
695Tick
696DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
697{
698 return tc->getCpuPtr()->ticks(1);
699}
700

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