tlb.cc (5881:73c0aaaaf186) tlb.cc (5891:73084c6bb183)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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185 if (entry != entryList.end()) {
186 freeList.push_back(*entry);
187 entryList.erase(entry);
188 }
189}
190
191template<class TlbFault>
192Fault
193TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
193TLB::translateAtomic(RequestPtr &req, ThreadContext *tc,
194 bool write, bool execute)
194{
195 Addr vaddr = req->getVaddr();
196 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
197 uint32_t flags = req->getFlags();
198 bool storeCheck = flags & StoreCheck;
199
200 int seg = flags & mask(4);
201

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657 req->setFlags(Request::UNCACHEABLE);
658 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
659 }
660#endif
661 return NoFault;
662};
663
664Fault
195{
196 Addr vaddr = req->getVaddr();
197 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
198 uint32_t flags = req->getFlags();
199 bool storeCheck = flags & StoreCheck;
200
201 int seg = flags & mask(4);
202

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658 req->setFlags(Request::UNCACHEABLE);
659 req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
660 }
661#endif
662 return NoFault;
663};
664
665Fault
665DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
666DTB::translateAtomic(RequestPtr &req, ThreadContext *tc, bool write)
666{
667{
667 return TLB::translate(req, tc, write, false);
668 return TLB::translateAtomic<FakeDTLBFault>(req, tc, write, false);
668}
669
670Fault
669}
670
671Fault
671ITB::translate(RequestPtr &req, ThreadContext *tc)
672ITB::translateAtomic(RequestPtr &req, ThreadContext *tc)
672{
673{
673 return TLB::translate(req, tc, false, true);
674 return TLB::translateAtomic<FakeITLBFault>(req, tc, false, true);
674}
675
676#if FULL_SYSTEM
677
678Tick
679DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
680{
681 return tc->getCpuPtr()->ticks(1);

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676
677#if FULL_SYSTEM
678
679Tick
680DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
681{
682 return tc->getCpuPtr()->ticks(1);

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