tlb.cc (5440:51d24253bcd9) tlb.cc (5647:b06b49498c79)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

--- 649 unchanged lines hidden (view full) ---

658 if ((paddr & ~mask(3)) != ((paddr + req->getSize()) & ~mask(3)))
659 panic("Accessed more than one register at a time in the APIC!\n");
660 MiscReg regNum;
661 Addr offset = paddr & mask(3);
662 paddr &= ~mask(3);
663 switch (paddr - baseAddr)
664 {
665 case 0x20:
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

--- 649 unchanged lines hidden (view full) ---

658 if ((paddr & ~mask(3)) != ((paddr + req->getSize()) & ~mask(3)))
659 panic("Accessed more than one register at a time in the APIC!\n");
660 MiscReg regNum;
661 Addr offset = paddr & mask(3);
662 paddr &= ~mask(3);
663 switch (paddr - baseAddr)
664 {
665 case 0x20:
666 regNum = MISCREG_APIC_ID;
666 regNum = APIC_ID;
667 break;
668 case 0x30:
667 break;
668 case 0x30:
669 regNum = MISCREG_APIC_VERSION;
669 regNum = APIC_VERSION;
670 break;
671 case 0x80:
670 break;
671 case 0x80:
672 regNum = MISCREG_APIC_TASK_PRIORITY;
672 regNum = APIC_TASK_PRIORITY;
673 break;
674 case 0x90:
673 break;
674 case 0x90:
675 regNum = MISCREG_APIC_ARBITRATION_PRIORITY;
675 regNum = APIC_ARBITRATION_PRIORITY;
676 break;
677 case 0xA0:
676 break;
677 case 0xA0:
678 regNum = MISCREG_APIC_PROCESSOR_PRIORITY;
678 regNum = APIC_PROCESSOR_PRIORITY;
679 break;
680 case 0xB0:
679 break;
680 case 0xB0:
681 regNum = MISCREG_APIC_EOI;
681 regNum = APIC_EOI;
682 break;
683 case 0xD0:
682 break;
683 case 0xD0:
684 regNum = MISCREG_APIC_LOGICAL_DESTINATION;
684 regNum = APIC_LOGICAL_DESTINATION;
685 break;
686 case 0xE0:
685 break;
686 case 0xE0:
687 regNum = MISCREG_APIC_DESTINATION_FORMAT;
687 regNum = APIC_DESTINATION_FORMAT;
688 break;
689 case 0xF0:
688 break;
689 case 0xF0:
690 regNum = MISCREG_APIC_SPURIOUS_INTERRUPT_VECTOR;
690 regNum = APIC_SPURIOUS_INTERRUPT_VECTOR;
691 break;
692 case 0x100:
693 case 0x108:
694 case 0x110:
695 case 0x118:
696 case 0x120:
697 case 0x128:
698 case 0x130:
699 case 0x138:
700 case 0x140:
701 case 0x148:
702 case 0x150:
703 case 0x158:
704 case 0x160:
705 case 0x168:
706 case 0x170:
707 case 0x178:
691 break;
692 case 0x100:
693 case 0x108:
694 case 0x110:
695 case 0x118:
696 case 0x120:
697 case 0x128:
698 case 0x130:
699 case 0x138:
700 case 0x140:
701 case 0x148:
702 case 0x150:
703 case 0x158:
704 case 0x160:
705 case 0x168:
706 case 0x170:
707 case 0x178:
708 regNum = MISCREG_APIC_IN_SERVICE(
709 (paddr - baseAddr - 0x100) / 0x8);
708 regNum = APIC_IN_SERVICE((paddr - baseAddr - 0x100) / 0x8);
710 break;
711 case 0x180:
712 case 0x188:
713 case 0x190:
714 case 0x198:
715 case 0x1A0:
716 case 0x1A8:
717 case 0x1B0:
718 case 0x1B8:
719 case 0x1C0:
720 case 0x1C8:
721 case 0x1D0:
722 case 0x1D8:
723 case 0x1E0:
724 case 0x1E8:
725 case 0x1F0:
726 case 0x1F8:
709 break;
710 case 0x180:
711 case 0x188:
712 case 0x190:
713 case 0x198:
714 case 0x1A0:
715 case 0x1A8:
716 case 0x1B0:
717 case 0x1B8:
718 case 0x1C0:
719 case 0x1C8:
720 case 0x1D0:
721 case 0x1D8:
722 case 0x1E0:
723 case 0x1E8:
724 case 0x1F0:
725 case 0x1F8:
727 regNum = MISCREG_APIC_TRIGGER_MODE(
728 (paddr - baseAddr - 0x180) / 0x8);
726 regNum = APIC_TRIGGER_MODE((paddr - baseAddr - 0x180) / 0x8);
729 break;
730 case 0x200:
731 case 0x208:
732 case 0x210:
733 case 0x218:
734 case 0x220:
735 case 0x228:
736 case 0x230:
737 case 0x238:
738 case 0x240:
739 case 0x248:
740 case 0x250:
741 case 0x258:
742 case 0x260:
743 case 0x268:
744 case 0x270:
745 case 0x278:
727 break;
728 case 0x200:
729 case 0x208:
730 case 0x210:
731 case 0x218:
732 case 0x220:
733 case 0x228:
734 case 0x230:
735 case 0x238:
736 case 0x240:
737 case 0x248:
738 case 0x250:
739 case 0x258:
740 case 0x260:
741 case 0x268:
742 case 0x270:
743 case 0x278:
746 regNum = MISCREG_APIC_INTERRUPT_REQUEST(
747 (paddr - baseAddr - 0x200) / 0x8);
744 regNum = APIC_INTERRUPT_REQUEST((paddr - baseAddr - 0x200) / 0x8);
748 break;
749 case 0x280:
745 break;
746 case 0x280:
750 regNum = MISCREG_APIC_ERROR_STATUS;
747 regNum = APIC_ERROR_STATUS;
751 break;
752 case 0x300:
748 break;
749 case 0x300:
753 regNum = MISCREG_APIC_INTERRUPT_COMMAND_LOW;
750 regNum = APIC_INTERRUPT_COMMAND_LOW;
754 break;
755 case 0x310:
751 break;
752 case 0x310:
756 regNum = MISCREG_APIC_INTERRUPT_COMMAND_HIGH;
753 regNum = APIC_INTERRUPT_COMMAND_HIGH;
757 break;
758 case 0x320:
754 break;
755 case 0x320:
759 regNum = MISCREG_APIC_LVT_TIMER;
756 regNum = APIC_LVT_TIMER;
760 break;
761 case 0x330:
757 break;
758 case 0x330:
762 regNum = MISCREG_APIC_LVT_THERMAL_SENSOR;
759 regNum = APIC_LVT_THERMAL_SENSOR;
763 break;
764 case 0x340:
760 break;
761 case 0x340:
765 regNum = MISCREG_APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
762 regNum = APIC_LVT_PERFORMANCE_MONITORING_COUNTERS;
766 break;
767 case 0x350:
763 break;
764 case 0x350:
768 regNum = MISCREG_APIC_LVT_LINT0;
765 regNum = APIC_LVT_LINT0;
769 break;
770 case 0x360:
766 break;
767 case 0x360:
771 regNum = MISCREG_APIC_LVT_LINT1;
768 regNum = APIC_LVT_LINT1;
772 break;
773 case 0x370:
769 break;
770 case 0x370:
774 regNum = MISCREG_APIC_LVT_ERROR;
771 regNum = APIC_LVT_ERROR;
775 break;
776 case 0x380:
772 break;
773 case 0x380:
777 regNum = MISCREG_APIC_INITIAL_COUNT;
774 regNum = APIC_INITIAL_COUNT;
778 break;
779 case 0x390:
775 break;
776 case 0x390:
780 regNum = MISCREG_APIC_CURRENT_COUNT;
777 regNum = APIC_CURRENT_COUNT;
781 break;
782 case 0x3E0:
778 break;
779 case 0x3E0:
783 regNum = MISCREG_APIC_DIVIDE_CONFIGURATION;
780 regNum = APIC_DIVIDE_CONFIGURATION;
784 break;
785 default:
786 // A reserved register field.
787 return new GeneralProtection(0);
788 break;
789 }
781 break;
782 default:
783 // A reserved register field.
784 return new GeneralProtection(0);
785 break;
786 }
787 regNum += MISCREG_APIC_START;
790 req->setPaddr(regNum * sizeof(MiscReg) + offset);
791 }
792#endif
793 return NoFault;
794};
795
796Fault
797DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)

--- 61 unchanged lines hidden --- 		788 req->setPaddr(regNum * sizeof(MiscReg) + offset);
789 }
790#endif
791 return NoFault;
792};
793
794Fault
795DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)

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