tlb.cc (5236:0050ad4fb3ef) tlb.cc (5237:6c819dbe8045)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "config/full_system.hh"
67#include "cpu/thread_context.hh"
68#include "cpu/base.hh"
69#include "mem/packet_access.hh"
70#include "mem/request.hh"
71#include "sim/system.hh"
72
73namespace X86ISA {
74
68#include "cpu/thread_context.hh"
69#include "cpu/base.hh"
70#include "mem/packet_access.hh"
71#include "mem/request.hh"
72#include "sim/system.hh"
73
74namespace X86ISA {
75
76#if FULL_SYSTEM
75TLB::TLB(const Params *p) : MemObject(p), walker(name(), this), size(p->size)
77TLB::TLB(const Params *p) : MemObject(p), walker(name(), this), size(p->size)
78#else
79TLB::TLB(const Params *p) : MemObject(p), size(p->size)
80#endif
76{
77 tlb = new TlbEntry[size];
78 std::memset(tlb, 0, sizeof(TlbEntry) * size);
79
80 for (int x = 0; x < size; x++)
81 freeList.push_back(&tlb[x]);
82}
83
81{
82 tlb = new TlbEntry[size];
83 std::memset(tlb, 0, sizeof(TlbEntry) * size);
84
85 for (int x = 0; x < size; x++)
86 freeList.push_back(&tlb[x]);
87}
88
84bool
85TLB::Walker::doNext(uint64_t data, PacketPtr &write)
89#if FULL_SYSTEM
90
91// Unfortunately, the placement of the base field in a page table entry is
92// very erratic and would make a mess here. It might be moved here at some
93// point in the future.
94BitUnion64(PageTableEntry)
95 Bitfield<63> nx;
96 Bitfield<11, 9> avl;
97 Bitfield<8> g;
98 Bitfield<7> ps;
99 Bitfield<6> d;
100 Bitfield<5> a;
101 Bitfield<4> pcd;
102 Bitfield<3> pwt;
103 Bitfield<2> u;
104 Bitfield<1> w;
105 Bitfield<0> p;
106EndBitUnion(PageTableEntry)
107
108void
109TLB::Walker::doNext(PacketPtr &read, PacketPtr &write)
86{
87 assert(state != Ready && state != Waiting);
88 write = NULL;
110{
111 assert(state != Ready && state != Waiting);
112 write = NULL;
113 PageTableEntry pte;
114 if (size == 8)
115 pte = read->get<uint64_t>();
116 else
117 pte = read->get<uint32_t>();
118 VAddr vaddr = entry.vaddr;
119 bool uncacheable = pte.pcd;
120 Addr nextRead = 0;
121 bool doWrite = false;
122 bool badNX = pte.nx && (!tlb->allowNX || !enableNX);
89 switch(state) {
90 case LongPML4:
123 switch(state) {
124 case LongPML4:
125 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl3 * size;
126 doWrite = !pte.a;
127 pte.a = 1;
128 entry.writable = pte.w;
129 entry.user = pte.u;
130 if (badNX)
131 panic("NX violation!\n");
132 entry.noExec = pte.nx;
133 if (!pte.p)
134 panic("Page not present!\n");
91 nextState = LongPDP;
92 break;
93 case LongPDP:
135 nextState = LongPDP;
136 break;
137 case LongPDP:
138 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl2 * size;
139 doWrite = !pte.a;
140 pte.a = 1;
141 entry.writable = entry.writable && pte.w;
142 entry.user = entry.user && pte.u;
143 if (badNX)
144 panic("NX violation!\n");
145 if (!pte.p)
146 panic("Page not present!\n");
94 nextState = LongPD;
95 break;
96 case LongPD:
147 nextState = LongPD;
148 break;
149 case LongPD:
97 nextState = LongPTE;
98 break;
150 doWrite = !pte.a;
151 pte.a = 1;
152 entry.writable = entry.writable && pte.w;
153 entry.user = entry.user && pte.u;
154 if (badNX)
155 panic("NX violation!\n");
156 if (!pte.p)
157 panic("Page not present!\n");
158 if (!pte.ps) {
159 // 4 KB page
160 entry.size = 4 * (1 << 10);
161 nextRead =
162 ((uint64_t)pte & (mask(40) << 12)) + vaddr.longl1 * size;
163 nextState = LongPTE;
164 break;
165 } else {
166 // 2 MB page
167 entry.size = 2 * (1 << 20);
168 entry.paddr = (uint64_t)pte & (mask(31) << 21);
169 entry.uncacheable = uncacheable;
170 entry.global = pte.g;
171 entry.patBit = bits(pte, 12);
172 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
173 tlb->insert(entry.vaddr, entry);
174 nextState = Ready;
175 delete read->req;
176 delete read;
177 read = NULL;
178 return;
179 }
99 case LongPTE:
180 case LongPTE:
181 doWrite = !pte.a;
182 pte.a = 1;
183 entry.writable = entry.writable && pte.w;
184 entry.user = entry.user && pte.u;
185 if (badNX)
186 panic("NX violation!\n");
187 if (!pte.p)
188 panic("Page not present!\n");
189 entry.paddr = (uint64_t)pte & (mask(40) << 12);
190 entry.uncacheable = uncacheable;
191 entry.global = pte.g;
192 entry.patBit = bits(pte, 12);
193 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
194 tlb->insert(entry.vaddr, entry);
100 nextState = Ready;
195 nextState = Ready;
101 return false;
196 delete read->req;
197 delete read;
198 read = NULL;
199 return;
102 case PAEPDP:
200 case PAEPDP:
201 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael2 * size;
202 if (!pte.p)
203 panic("Page not present!\n");
103 nextState = PAEPD;
104 break;
105 case PAEPD:
204 nextState = PAEPD;
205 break;
206 case PAEPD:
106 break;
207 doWrite = !pte.a;
208 pte.a = 1;
209 entry.writable = pte.w;
210 entry.user = pte.u;
211 if (badNX)
212 panic("NX violation!\n");
213 if (!pte.p)
214 panic("Page not present!\n");
215 if (!pte.ps) {
216 // 4 KB page
217 entry.size = 4 * (1 << 10);
218 nextRead = ((uint64_t)pte & (mask(40) << 12)) + vaddr.pael1 * size;
219 nextState = PAEPTE;
220 break;
221 } else {
222 // 2 MB page
223 entry.size = 2 * (1 << 20);
224 entry.paddr = (uint64_t)pte & (mask(31) << 21);
225 entry.uncacheable = uncacheable;
226 entry.global = pte.g;
227 entry.patBit = bits(pte, 12);
228 entry.vaddr = entry.vaddr & ~((2 * (1 << 20)) - 1);
229 tlb->insert(entry.vaddr, entry);
230 nextState = Ready;
231 delete read->req;
232 delete read;
233 read = NULL;
234 return;
235 }
107 case PAEPTE:
236 case PAEPTE:
237 doWrite = !pte.a;
238 pte.a = 1;
239 entry.writable = entry.writable && pte.w;
240 entry.user = entry.user && pte.u;
241 if (badNX)
242 panic("NX violation!\n");
243 if (!pte.p)
244 panic("Page not present!\n");
245 entry.paddr = (uint64_t)pte & (mask(40) << 12);
246 entry.uncacheable = uncacheable;
247 entry.global = pte.g;
248 entry.patBit = bits(pte, 7);
249 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
250 tlb->insert(entry.vaddr, entry);
108 nextState = Ready;
251 nextState = Ready;
109 return false;
252 delete read->req;
253 delete read;
254 read = NULL;
255 return;
110 case PSEPD:
256 case PSEPD:
111 break;
257 doWrite = !pte.a;
258 pte.a = 1;
259 entry.writable = pte.w;
260 entry.user = pte.u;
261 if (!pte.p)
262 panic("Page not present!\n");
263 if (!pte.ps) {
264 // 4 KB page
265 entry.size = 4 * (1 << 10);
266 nextRead =
267 ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * size;
268 nextState = PTE;
269 break;
270 } else {
271 // 4 MB page
272 entry.size = 4 * (1 << 20);
273 entry.paddr = bits(pte, 20, 13) << 32 | bits(pte, 31, 22) << 22;
274 entry.uncacheable = uncacheable;
275 entry.global = pte.g;
276 entry.patBit = bits(pte, 12);
277 entry.vaddr = entry.vaddr & ~((4 * (1 << 20)) - 1);
278 tlb->insert(entry.vaddr, entry);
279 nextState = Ready;
280 delete read->req;
281 delete read;
282 read = NULL;
283 return;
284 }
112 case PD:
285 case PD:
286 doWrite = !pte.a;
287 pte.a = 1;
288 entry.writable = pte.w;
289 entry.user = pte.u;
290 if (!pte.p)
291 panic("Page not present!\n");
292 // 4 KB page
293 entry.size = 4 * (1 << 10);
294 nextRead = ((uint64_t)pte & (mask(20) << 12)) + vaddr.norml2 * size;
113 nextState = PTE;
114 break;
295 nextState = PTE;
296 break;
297 nextState = PTE;
298 break;
115 case PTE:
299 case PTE:
300 doWrite = !pte.a;
301 pte.a = 1;
302 entry.writable = pte.w;
303 entry.user = pte.u;
304 if (!pte.p)
305 panic("Page not present!\n");
306 entry.paddr = (uint64_t)pte & (mask(20) << 12);
307 entry.uncacheable = uncacheable;
308 entry.global = pte.g;
309 entry.patBit = bits(pte, 7);
310 entry.vaddr = entry.vaddr & ~((4 * (1 << 10)) - 1);
311 tlb->insert(entry.vaddr, entry);
116 nextState = Ready;
312 nextState = Ready;
117 return false;
313 delete read->req;
314 delete read;
315 read = NULL;
316 return;
118 default:
119 panic("Unknown page table walker state %d!\n");
120 }
317 default:
318 panic("Unknown page table walker state %d!\n");
319 }
121 return true;
320 PacketPtr oldRead = read;
321 //If we didn't return, we're setting up another read.
322 uint32_t flags = oldRead->req->getFlags();
323 if (uncacheable)
324 flags |= UNCACHEABLE;
325 else
326 flags &= ~UNCACHEABLE;
327 RequestPtr request =
328 new Request(nextRead, oldRead->getSize(), flags);
329 read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast);
330 read->allocate();
331 //If we need to write, adjust the read packet to write the modified value
332 //back to memory.
333 if (doWrite) {
334 write = oldRead;
335 write->set<uint64_t>(pte);
336 write->cmd = MemCmd::WriteReq;
337 write->setDest(Packet::Broadcast);
338 } else {
339 write = NULL;
340 delete oldRead->req;
341 delete oldRead;
342 }
122}
123
124void
343}
344
345void
125TLB::Walker::buildReadPacket(Addr addr)
346TLB::Walker::start(ThreadContext * _tc, Addr vaddr)
126{
347{
127 readRequest.setPhys(addr, size, PHYSICAL | uncachable ? UNCACHEABLE : 0);
128 readPacket.reinitFromRequest();
348 assert(state == Ready);
349 assert(!tc);
350 tc = _tc;
351
352 VAddr addr = vaddr;
353
354 //Figure out what we're doing.
355 CR3 cr3 = tc->readMiscRegNoEffect(MISCREG_CR3);
356 Addr top = 0;
357 // Check if we're in long mode or not
358 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
359 size = 8;
360 if (efer.lma) {
361 // Do long mode.
362 state = LongPML4;
363 top = (cr3.longPdtb << 12) + addr.longl4 * size;
364 } else {
365 // We're in some flavor of legacy mode.
366 CR4 cr4 = tc->readMiscRegNoEffect(MISCREG_CR4);
367 if (cr4.pae) {
368 // Do legacy PAE.
369 state = PAEPDP;
370 top = (cr3.paePdtb << 5) + addr.pael3 * size;
371 } else {
372 size = 4;
373 top = (cr3.pdtb << 12) + addr.norml2 * size;
374 if (cr4.pse) {
375 // Do legacy PSE.
376 state = PSEPD;
377 } else {
378 // Do legacy non PSE.
379 state = PD;
380 }
381 }
382 }
383 nextState = Ready;
384 entry.vaddr = vaddr;
385
386 enableNX = efer.nxe;
387
388 RequestPtr request =
389 new Request(top, size, PHYSICAL | cr3.pcd ? UNCACHEABLE : 0);
390 read = new Packet(request, MemCmd::ReadExReq, Packet::Broadcast);
391 read->allocate();
392 Enums::MemoryMode memMode = tlb->sys->getMemoryMode();
393 if (memMode == Enums::timing) {
394 tc->suspend();
395 port.sendTiming(read);
396 } else if (memMode == Enums::atomic) {
397 do {
398 port.sendAtomic(read);
399 PacketPtr write = NULL;
400 doNext(read, write);
401 state = nextState;
402 nextState = Ready;
403 if (write)
404 port.sendAtomic(write);
405 } while(read);
406 tc = NULL;
407 state = Ready;
408 nextState = Waiting;
409 } else {
410 panic("Unrecognized memory system mode.\n");
411 }
129}
130
412}
413
131TLB::walker::buildWritePacket(Addr addr)
414bool
415TLB::Walker::WalkerPort::recvTiming(PacketPtr pkt)
132{
416{
133 writeRequest.setPhys(addr, size, PHYSICAL | uncachable ? UNCACHEABLE : 0);
134 writePacket.reinitFromRequest();
417 return walker->recvTiming(pkt);
418}
135
136bool
419
420bool
137TLB::Walker::WalkerPort::recvTiming(PacketPtr pkt)
421TLB::Walker::recvTiming(PacketPtr pkt)
138{
422{
423 inflight--;
139 if (pkt->isResponse() && !pkt->wasNacked()) {
140 if (pkt->isRead()) {
424 if (pkt->isResponse() && !pkt->wasNacked()) {
425 if (pkt->isRead()) {
141 assert(packet);
142 assert(walker->state == Waiting);
143 packet = NULL;
144 walker->state = walker->nextState;
145 walker->nextState = Ready;
146 PacketPtr write;
147 if (walker->doNext(pkt, write)) {
148 packet = &walker->packet;
149 port->sendTiming(packet);
150 }
426 assert(inflight);
427 assert(state == Waiting);
428 assert(!read);
429 state = nextState;
430 nextState = Ready;
431 PacketPtr write = NULL;
432 doNext(pkt, write);
433 state = Waiting;
434 read = pkt;
151 if (write) {
152 writes.push_back(write);
153 }
435 if (write) {
436 writes.push_back(write);
437 }
154 while (!port->blocked() && writes.size()) {
155 if (port->sendTiming(writes.front())) {
156 writes.pop_front();
157 outstandingWrites++;
158 }
159 }
438 sendPackets();
160 } else {
439 } else {
161 outstandingWrites--;
440 sendPackets();
162 }
441 }
442 if (inflight == 0 && read == NULL && writes.size() == 0) {
443 tc->activate(0);
444 tc = NULL;
445 state = Ready;
446 nextState = Waiting;
447 }
163 } else if (pkt->wasNacked()) {
164 pkt->reinitNacked();
448 } else if (pkt->wasNacked()) {
449 pkt->reinitNacked();
165 if (!sendTiming(pkt)) {
450 if (!port.sendTiming(pkt)) {
451 retrying = true;
166 if (pkt->isWrite()) {
452 if (pkt->isWrite()) {
167 writes.push_front(pkt);
453 writes.push_back(pkt);
454 } else {
455 assert(!read);
456 read = pkt;
168 }
457 }
458 } else {
459 inflight++;
169 }
170 }
171 return true;
172}
173
174Tick
175TLB::Walker::WalkerPort::recvAtomic(PacketPtr pkt)
176{

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195 }
196
197 panic("Unexpected recvStatusChange.\n");
198}
199
200void
201TLB::Walker::WalkerPort::recvRetry()
202{
460 }
461 }
462 return true;
463}
464
465Tick
466TLB::Walker::WalkerPort::recvAtomic(PacketPtr pkt)
467{

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486 }
487
488 panic("Unexpected recvStatusChange.\n");
489}
490
491void
492TLB::Walker::WalkerPort::recvRetry()
493{
494 walker->recvRetry();
495}
496
497void
498TLB::Walker::recvRetry()
499{
203 retrying = false;
500 retrying = false;
204 if (!sendTiming(packet)) {
205 retrying = true;
501 sendPackets();
502}
503
504void
505TLB::Walker::sendPackets()
506{
507 //If we're already waiting for the port to become available, just return.
508 if (retrying)
509 return;
510
511 //Reads always have priority
512 if (read) {
513 if (!port.sendTiming(read)) {
514 retrying = true;
515 return;
516 } else {
517 inflight++;
518 delete read->req;
519 delete read;
520 read = NULL;
521 }
206 }
522 }
523 //Send off as many of the writes as we can.
524 while (writes.size()) {
525 PacketPtr write = writes.back();
526 if (!port.sendTiming(write)) {
527 retrying = true;
528 return;
529 } else {
530 inflight++;
531 delete write->req;
532 delete write;
533 writes.pop_back();
534 }
535 }
207}
208
209Port *
210TLB::getPort(const std::string &if_name, int idx)
211{
212 if (if_name == "walker_port")
213 return &walker.port;
214 else
215 panic("No tlb port named %s!\n", if_name);
216}
217
536}
537
538Port *
539TLB::getPort(const std::string &if_name, int idx)
540{
541 if (if_name == "walker_port")
542 return &walker.port;
543 else
544 panic("No tlb port named %s!\n", if_name);
545}
546
547#else
548
549Port *
550TLB::getPort(const std::string &if_name, int idx)
551{
552 panic("No tlb ports in se!\n", if_name);
553}
554
555#endif
556
218void
219TLB::insert(Addr vpn, TlbEntry &entry)
220{
221 //TODO Deal with conflicting entries
222
223 TlbEntry *newEntry = NULL;
224 if (!freeList.empty()) {
225 newEntry = freeList.front();

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577 }
578
579 // Get cr0. This will tell us how to do translation. We'll assume it was
580 // verified to be correct and consistent when set.
581 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
582
583 // If protected mode has been enabled...
584 if (cr0.pe) {
557void
558TLB::insert(Addr vpn, TlbEntry &entry)
559{
560 //TODO Deal with conflicting entries
561
562 TlbEntry *newEntry = NULL;
563 if (!freeList.empty()) {
564 newEntry = freeList.front();

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916 }
917
918 // Get cr0. This will tell us how to do translation. We'll assume it was
919 // verified to be correct and consistent when set.
920 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
921
922 // If protected mode has been enabled...
923 if (cr0.pe) {
924 DPRINTF(TLB, "In protected mode.\n");
585 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
586 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
587 // If we're not in 64-bit mode, do protection/limit checks
588 if (!efer.lma || !csAttr.longMode) {
925 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
926 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);
927 // If we're not in 64-bit mode, do protection/limit checks
928 if (!efer.lma || !csAttr.longMode) {
929 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n");
589 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
590 if (!attr.writable && write)
591 return new GeneralProtection(0);
592 if (!attr.readable && !write && !execute)
593 return new GeneralProtection(0);
594 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
595 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
596 if (!attr.expandDown) {
930 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg));
931 if (!attr.writable && write)
932 return new GeneralProtection(0);
933 if (!attr.readable && !write && !execute)
934 return new GeneralProtection(0);
935 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg));
936 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg));
937 if (!attr.expandDown) {
938 DPRINTF(TLB, "Checking an expand down segment.\n");
597 // We don't have to worry about the access going around the
598 // end of memory because accesses will be broken up into
599 // pieces at boundaries aligned on sizes smaller than an
600 // entire address space. We do have to worry about the limit
601 // being less than the base.
602 if (limit < base) {
603 if (limit < vaddr + req->getSize() && vaddr < base)
604 return new GeneralProtection(0);

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613 } else {
614 if (vaddr <= limit && vaddr + req->getSize() >= base)
615 return new GeneralProtection(0);
616 }
617 }
618 }
619 // If paging is enabled, do the translation.
620 if (cr0.pg) {
939 // We don't have to worry about the access going around the
940 // end of memory because accesses will be broken up into
941 // pieces at boundaries aligned on sizes smaller than an
942 // entire address space. We do have to worry about the limit
943 // being less than the base.
944 if (limit < base) {
945 if (limit < vaddr + req->getSize() && vaddr < base)
946 return new GeneralProtection(0);

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955 } else {
956 if (vaddr <= limit && vaddr + req->getSize() >= base)
957 return new GeneralProtection(0);
958 }
959 }
960 }
961 // If paging is enabled, do the translation.
962 if (cr0.pg) {
963 DPRINTF(TLB, "Paging enabled.\n");
621 // The vaddr already has the segment base applied.
622 TlbEntry *entry = lookup(vaddr);
623 if (!entry) {
964 // The vaddr already has the segment base applied.
965 TlbEntry *entry = lookup(vaddr);
966 if (!entry) {
624#if FULL_SYSTEM
625 return new TlbFault();
626#else
627 return new TlbFault(vaddr);
967 return new TlbFault(vaddr);
628#endif
629 } else {
630 // Do paging protection checks.
968 } else {
969 // Do paging protection checks.
631 Addr paddr = entry->paddr | (vaddr & mask(12));
970 DPRINTF(TLB, "Entry found with paddr %#x, doing protection checks.\n", entry->paddr);
971 Addr paddr = entry->paddr | (vaddr & (entry->size-1));
972 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
632 req->setPaddr(paddr);
633 }
634 } else {
635 //Use the address which already has segmentation applied.
973 req->setPaddr(paddr);
974 }
975 } else {
976 //Use the address which already has segmentation applied.
977 DPRINTF(TLB, "Paging disabled.\n");
978 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
636 req->setPaddr(vaddr);
637 }
638 } else {
639 // Real mode
979 req->setPaddr(vaddr);
980 }
981 } else {
982 // Real mode
983 DPRINTF(TLB, "In real mode.\n");
984 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
640 req->setPaddr(vaddr);
641 }
642 return NoFault;
643};
644
645Fault
646DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
647{

--- 60 unchanged lines hidden --- 		985 req->setPaddr(vaddr);
986 }
987 return NoFault;
988};
989
990Fault
991DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
992{

--- 60 unchanged lines hidden ---