tlb.cc (5140:2fd7f8477b4c) tlb.cc (5149:356e00996637)
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
1/*
2 * Copyright (c) 2007 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * Redistribution and use of this software in source and binary forms,
6 * with or without modification, are permitted provided that the
7 * following conditions are met:
8 *

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56 */
57
58#include <cstring>
59
60#include "config/full_system.hh"
61
62#include "arch/x86/pagetable.hh"
63#include "arch/x86/tlb.hh"
64#include "arch/x86/x86_traits.hh"
64#include "base/bitfield.hh"
65#include "base/trace.hh"
66#include "cpu/thread_context.hh"
67#include "cpu/base.hh"
68#include "mem/packet_access.hh"
69#include "mem/request.hh"
70#include "sim/system.hh"
71

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137Fault
138TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
139{
140 Addr vaddr = req->getVaddr();
141 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
142 uint32_t flags = req->getFlags();
143 bool storeCheck = flags & StoreCheck;
144
65#include "base/bitfield.hh"
66#include "base/trace.hh"
67#include "cpu/thread_context.hh"
68#include "cpu/base.hh"
69#include "mem/packet_access.hh"
70#include "mem/request.hh"
71#include "sim/system.hh"
72

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138Fault
139TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
140{
141 Addr vaddr = req->getVaddr();
142 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr);
143 uint32_t flags = req->getFlags();
144 bool storeCheck = flags & StoreCheck;
145
145 int seg = flags & (mask(NUM_SEGMENTREGS));
146 int seg = flags & mask(3);
146
147 //XXX Junk code to surpress the warning
147
148 //XXX Junk code to surpress the warning
148 if (storeCheck) seg = seg;
149 if (storeCheck);
149
150
151 // If this is true, we're dealing with a request to read an internal
152 // value.
153 if (seg == NUM_SEGMENTREGS) {
154 Addr prefix = vaddr & IntAddrPrefixMask;
155 if (prefix == IntAddrPrefixCPUID) {
156 panic("CPUID memory space not yet implemented!\n");
157 } else if (prefix == IntAddrPrefixMSR) {
158 req->setMmapedIpr(true);
159 Addr regNum = 0;
160 switch (vaddr & ~IntAddrPrefixMask) {
161 case 0x10:
162 regNum = MISCREG_TSC;
163 break;
164 case 0xFE:
165 regNum = MISCREG_MTRRCAP;
166 break;
167 case 0x174:
168 regNum = MISCREG_SYSENTER_CS;
169 break;
170 case 0x175:
171 regNum = MISCREG_SYSENTER_ESP;
172 break;
173 case 0x176:
174 regNum = MISCREG_SYSENTER_EIP;
175 break;
176 case 0x179:
177 regNum = MISCREG_MCG_CAP;
178 break;
179 case 0x17A:
180 regNum = MISCREG_MCG_STATUS;
181 break;
182 case 0x17B:
183 regNum = MISCREG_MCG_CTL;
184 break;
185 case 0x1D9:
186 regNum = MISCREG_DEBUG_CTL_MSR;
187 break;
188 case 0x1DB:
189 regNum = MISCREG_LAST_BRANCH_FROM_IP;
190 break;
191 case 0x1DC:
192 regNum = MISCREG_LAST_BRANCH_TO_IP;
193 break;
194 case 0x1DD:
195 regNum = MISCREG_LAST_EXCEPTION_FROM_IP;
196 break;
197 case 0x1DE:
198 regNum = MISCREG_LAST_EXCEPTION_TO_IP;
199 break;
200 case 0x200:
201 regNum = MISCREG_MTRR_PHYS_BASE_0;
202 break;
203 case 0x201:
204 regNum = MISCREG_MTRR_PHYS_MASK_0;
205 break;
206 case 0x202:
207 regNum = MISCREG_MTRR_PHYS_BASE_1;
208 break;
209 case 0x203:
210 regNum = MISCREG_MTRR_PHYS_MASK_1;
211 break;
212 case 0x204:
213 regNum = MISCREG_MTRR_PHYS_BASE_2;
214 break;
215 case 0x205:
216 regNum = MISCREG_MTRR_PHYS_MASK_2;
217 break;
218 case 0x206:
219 regNum = MISCREG_MTRR_PHYS_BASE_3;
220 break;
221 case 0x207:
222 regNum = MISCREG_MTRR_PHYS_MASK_3;
223 break;
224 case 0x208:
225 regNum = MISCREG_MTRR_PHYS_BASE_4;
226 break;
227 case 0x209:
228 regNum = MISCREG_MTRR_PHYS_MASK_4;
229 break;
230 case 0x20A:
231 regNum = MISCREG_MTRR_PHYS_BASE_5;
232 break;
233 case 0x20B:
234 regNum = MISCREG_MTRR_PHYS_MASK_5;
235 break;
236 case 0x20C:
237 regNum = MISCREG_MTRR_PHYS_BASE_6;
238 break;
239 case 0x20D:
240 regNum = MISCREG_MTRR_PHYS_MASK_6;
241 break;
242 case 0x20E:
243 regNum = MISCREG_MTRR_PHYS_BASE_7;
244 break;
245 case 0x20F:
246 regNum = MISCREG_MTRR_PHYS_MASK_7;
247 break;
248 case 0x250:
249 regNum = MISCREG_MTRR_FIX_64K_00000;
250 break;
251 case 0x258:
252 regNum = MISCREG_MTRR_FIX_16K_80000;
253 break;
254 case 0x259:
255 regNum = MISCREG_MTRR_FIX_16K_A0000;
256 break;
257 case 0x268:
258 regNum = MISCREG_MTRR_FIX_4K_C0000;
259 break;
260 case 0x269:
261 regNum = MISCREG_MTRR_FIX_4K_C8000;
262 break;
263 case 0x26A:
264 regNum = MISCREG_MTRR_FIX_4K_D0000;
265 break;
266 case 0x26B:
267 regNum = MISCREG_MTRR_FIX_4K_D8000;
268 break;
269 case 0x26C:
270 regNum = MISCREG_MTRR_FIX_4K_E0000;
271 break;
272 case 0x26D:
273 regNum = MISCREG_MTRR_FIX_4K_E8000;
274 break;
275 case 0x26E:
276 regNum = MISCREG_MTRR_FIX_4K_F0000;
277 break;
278 case 0x26F:
279 regNum = MISCREG_MTRR_FIX_4K_F8000;
280 break;
281 case 0x277:
282 regNum = MISCREG_PAT;
283 break;
284 case 0x2FF:
285 regNum = MISCREG_DEF_TYPE;
286 break;
287 case 0x400:
288 regNum = MISCREG_MC0_CTL;
289 break;
290 case 0x404:
291 regNum = MISCREG_MC1_CTL;
292 break;
293 case 0x408:
294 regNum = MISCREG_MC2_CTL;
295 break;
296 case 0x40C:
297 regNum = MISCREG_MC3_CTL;
298 break;
299 case 0x410:
300 regNum = MISCREG_MC4_CTL;
301 break;
302 case 0x401:
303 regNum = MISCREG_MC0_STATUS;
304 break;
305 case 0x405:
306 regNum = MISCREG_MC1_STATUS;
307 break;
308 case 0x409:
309 regNum = MISCREG_MC2_STATUS;
310 break;
311 case 0x40D:
312 regNum = MISCREG_MC3_STATUS;
313 break;
314 case 0x411:
315 regNum = MISCREG_MC4_STATUS;
316 break;
317 case 0x402:
318 regNum = MISCREG_MC0_ADDR;
319 break;
320 case 0x406:
321 regNum = MISCREG_MC1_ADDR;
322 break;
323 case 0x40A:
324 regNum = MISCREG_MC2_ADDR;
325 break;
326 case 0x40E:
327 regNum = MISCREG_MC3_ADDR;
328 break;
329 case 0x412:
330 regNum = MISCREG_MC4_ADDR;
331 break;
332 case 0x403:
333 regNum = MISCREG_MC0_MISC;
334 break;
335 case 0x407:
336 regNum = MISCREG_MC1_MISC;
337 break;
338 case 0x40B:
339 regNum = MISCREG_MC2_MISC;
340 break;
341 case 0x40F:
342 regNum = MISCREG_MC3_MISC;
343 break;
344 case 0x413:
345 regNum = MISCREG_MC4_MISC;
346 break;
347 case 0xC0000080:
348 regNum = MISCREG_EFER;
349 break;
350 case 0xC0000081:
351 regNum = MISCREG_STAR;
352 break;
353 case 0xC0000082:
354 regNum = MISCREG_LSTAR;
355 break;
356 case 0xC0000083:
357 regNum = MISCREG_CSTAR;
358 break;
359 case 0xC0000084:
360 regNum = MISCREG_SF_MASK;
361 break;
362 case 0xC0000100:
363 regNum = MISCREG_FS_BASE;
364 break;
365 case 0xC0000101:
366 regNum = MISCREG_GS_BASE;
367 break;
368 case 0xC0000102:
369 regNum = MISCREG_KERNEL_GS_BASE;
370 break;
371 case 0xC0000103:
372 regNum = MISCREG_TSC_AUX;
373 break;
374 case 0xC0010000:
375 regNum = MISCREG_PERF_EVT_SEL0;
376 break;
377 case 0xC0010001:
378 regNum = MISCREG_PERF_EVT_SEL1;
379 break;
380 case 0xC0010002:
381 regNum = MISCREG_PERF_EVT_SEL2;
382 break;
383 case 0xC0010003:
384 regNum = MISCREG_PERF_EVT_SEL3;
385 break;
386 case 0xC0010004:
387 regNum = MISCREG_PERF_EVT_CTR0;
388 break;
389 case 0xC0010005:
390 regNum = MISCREG_PERF_EVT_CTR1;
391 break;
392 case 0xC0010006:
393 regNum = MISCREG_PERF_EVT_CTR2;
394 break;
395 case 0xC0010007:
396 regNum = MISCREG_PERF_EVT_CTR3;
397 break;
398 case 0xC0010010:
399 regNum = MISCREG_SYSCFG;
400 break;
401 case 0xC0010016:
402 regNum = MISCREG_IORR_BASE0;
403 break;
404 case 0xC0010017:
405 regNum = MISCREG_IORR_BASE1;
406 break;
407 case 0xC0010018:
408 regNum = MISCREG_IORR_MASK0;
409 break;
410 case 0xC0010019:
411 regNum = MISCREG_IORR_MASK1;
412 break;
413 case 0xC001001A:
414 regNum = MISCREG_TOP_MEM;
415 break;
416 case 0xC001001D:
417 regNum = MISCREG_TOP_MEM2;
418 break;
419 case 0xC0010114:
420 regNum = MISCREG_VM_CR;
421 break;
422 case 0xC0010115:
423 regNum = MISCREG_IGNNE;
424 break;
425 case 0xC0010116:
426 regNum = MISCREG_SMM_CTL;
427 break;
428 case 0xC0010117:
429 regNum = MISCREG_VM_HSAVE_PA;
430 break;
431 default:
432 return new GeneralProtection(0);
433 }
434 //The index is multiplied by the size of a MiscReg so that
435 //any memory dependence calculations will not see these as
436 //overlapping.
437 req->setPaddr(regNum * sizeof(MiscReg));
438 return NoFault;
439 } else {
440 panic("Access to unrecognized internal address space %#x.\n",
441 prefix);
442 }
443 }
444
150 // Get cr0. This will tell us how to do translation. We'll assume it was
151 // verified to be correct and consistent when set.
152 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
153
154 // If protected mode has been enabled...
155 if (cr0.pe) {
156 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
157 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);

--- 121 unchanged lines hidden --- 		445 // Get cr0. This will tell us how to do translation. We'll assume it was
446 // verified to be correct and consistent when set.
447 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0);
448
449 // If protected mode has been enabled...
450 if (cr0.pe) {
451 Efer efer = tc->readMiscRegNoEffect(MISCREG_EFER);
452 SegAttr csAttr = tc->readMiscRegNoEffect(MISCREG_CS_ATTR);

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