tlb.cc (12461:a4cb506cda74) tlb.cc (12749:223c83ed9979)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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165 if (entry) {
166 trie.remove(entry->trieHandle);
167 entry->trieHandle = NULL;
168 freeList.push_back(entry);
169 }
170}
171
172Fault
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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165 if (entry) {
166 trie.remove(entry->trieHandle);
167 entry->trieHandle = NULL;
168 freeList.push_back(entry);
169 }
170}
171
172Fault
173TLB::translateInt(RequestPtr req, ThreadContext *tc)
173TLB::translateInt(const RequestPtr &req, ThreadContext *tc)
174{
175 DPRINTF(TLB, "Addresses references internal memory.\n");
176 Addr vaddr = req->getVaddr();
177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
178 if (prefix == IntAddrPrefixCPUID) {
179 panic("CPUID memory space not yet implemented!\n");
180 } else if (prefix == IntAddrPrefixMSR) {
181 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;

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219 return NoFault;
220 } else {
221 panic("Access to unrecognized internal address space %#x.\n",
222 prefix);
223 }
224}
225
226Fault
174{
175 DPRINTF(TLB, "Addresses references internal memory.\n");
176 Addr vaddr = req->getVaddr();
177 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask;
178 if (prefix == IntAddrPrefixCPUID) {
179 panic("CPUID memory space not yet implemented!\n");
180 } else if (prefix == IntAddrPrefixMSR) {
181 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask;

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219 return NoFault;
220 } else {
221 panic("Access to unrecognized internal address space %#x.\n",
222 prefix);
223 }
224}
225
226Fault
227TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
227TLB::finalizePhysical(const RequestPtr &req,
228 ThreadContext *tc, Mode mode) const
228{
229 Addr paddr = req->getPaddr();
230
231 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
232
233 if (m5opRange.contains(paddr)) {
234 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
235 Request::STRICT_ORDER);

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260 paddr - apicRange.start()));
261 }
262 }
263
264 return NoFault;
265}
266
267Fault
229{
230 Addr paddr = req->getPaddr();
231
232 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
233
234 if (m5opRange.contains(paddr)) {
235 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR |
236 Request::STRICT_ORDER);

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261 paddr - apicRange.start()));
262 }
263 }
264
265 return NoFault;
266}
267
268Fault
268TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
269TLB::translate(const RequestPtr &req,
270 ThreadContext *tc, Translation *translation,
269 Mode mode, bool &delayedResponse, bool timing)
270{
271 Request::Flags flags = req->getFlags();
272 int seg = flags & SegmentFlagMask;
273 bool storeCheck = flags & (StoreCheck << FlagShift);
274
275 delayedResponse = false;
276

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420 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
421 req->setPaddr(vaddr);
422 }
423
424 return finalizePhysical(req, tc, mode);
425}
426
427Fault
271 Mode mode, bool &delayedResponse, bool timing)
272{
273 Request::Flags flags = req->getFlags();
274 int seg = flags & SegmentFlagMask;
275 bool storeCheck = flags & (StoreCheck << FlagShift);
276
277 delayedResponse = false;
278

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422 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr);
423 req->setPaddr(vaddr);
424 }
425
426 return finalizePhysical(req, tc, mode);
427}
428
429Fault
428TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
430TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
429{
430 bool delayedResponse;
431 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
432}
433
434void
431{
432 bool delayedResponse;
433 return TLB::translate(req, tc, NULL, mode, delayedResponse, false);
434}
435
436void
435TLB::translateTiming(RequestPtr req, ThreadContext *tc,
437TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
436 Translation *translation, Mode mode)
437{
438 bool delayedResponse;
439 assert(translation);
440 Fault fault =
441 TLB::translate(req, tc, translation, mode, delayedResponse, true);
442 if (!delayedResponse)
443 translation->finish(fault, req, tc, mode);

--- 81 unchanged lines hidden --- 		438 Translation *translation, Mode mode)
439{
440 bool delayedResponse;
441 assert(translation);
442 Fault fault =
443 TLB::translate(req, tc, translation, mode, delayedResponse, true);
444 if (!delayedResponse)
445 translation->finish(fault, req, tc, mode);

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