tlb.cc (10474:799c8ee4ecba) tlb.cc (10553:c1ad57c53a36)
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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227 }
228}
229
230Fault
231TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
232{
233 Addr paddr = req->getPaddr();
234
1/*
2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 218 unchanged lines hidden (view full) ---

227 }
228}
229
230Fault
231TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const
232{
233 Addr paddr = req->getPaddr();
234
235 // Check for an access to the local APIC
236 if (FullSystem) {
235 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
236
237 if (m5opRange.contains(paddr)) {
238 if (m5opRange.contains(paddr)) {
239 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
240 req->setPaddr(GenericISA::iprAddressPseudoInst(
241 (paddr >> 8) & 0xFF,
242 paddr & 0xFF));
243 }
244 } else if (FullSystem) {
245 // Check for an access to the local APIC
237 LocalApicBase localApicBase =
238 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
239 AddrRange apicRange(localApicBase.base * PageBytes,
240 (localApicBase.base + 1) * PageBytes - 1);
241
246 LocalApicBase localApicBase =
247 tc->readMiscRegNoEffect(MISCREG_APIC_BASE);
248 AddrRange apicRange(localApicBase.base * PageBytes,
249 (localApicBase.base + 1) * PageBytes - 1);
250
242 AddrRange m5opRange(0xFFFF0000, 0xFFFFFFFF);
243
244 if (apicRange.contains(paddr)) {
245 // The Intel developer's manuals say the below restrictions apply,
246 // but the linux kernel, because of a compiler optimization, breaks
247 // them.
248 /*
249 // Check alignment
250 if (paddr & ((32/8) - 1))
251 return new GeneralProtection(0);
252 // Check access size
253 if (req->getSize() != (32/8))
254 return new GeneralProtection(0);
255 */
256 // Force the access to be uncacheable.
257 req->setFlags(Request::UNCACHEABLE);
258 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
259 paddr - apicRange.start()));
251 if (apicRange.contains(paddr)) {
252 // The Intel developer's manuals say the below restrictions apply,
253 // but the linux kernel, because of a compiler optimization, breaks
254 // them.
255 /*
256 // Check alignment
257 if (paddr & ((32/8) - 1))
258 return new GeneralProtection(0);
259 // Check access size
260 if (req->getSize() != (32/8))
261 return new GeneralProtection(0);
262 */
263 // Force the access to be uncacheable.
264 req->setFlags(Request::UNCACHEABLE);
265 req->setPaddr(x86LocalAPICAddress(tc->contextId(),
266 paddr - apicRange.start()));
260 } else if (m5opRange.contains(paddr)) {
261 req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR);
262 req->setPaddr(GenericISA::iprAddressPseudoInst(
263 (paddr >> 8) & 0xFF,
264 paddr & 0xFF));
265 }
266 }
267
268 return NoFault;
269}
270
271Fault
272TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,

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268 }
269
270 return NoFault;
271}
272
273Fault
274TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,

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