1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#include <cstring> 41 42#include "arch/x86/insts/microldstop.hh" 43#include "arch/x86/regs/misc.hh" 44#include "arch/x86/regs/msr.hh" 45#include "arch/x86/faults.hh" 46#include "arch/x86/pagetable.hh" 47#include "arch/x86/pagetable_walker.hh" 48#include "arch/x86/tlb.hh" 49#include "arch/x86/x86_traits.hh" 50#include "base/bitfield.hh" 51#include "base/trace.hh" 52#include "cpu/base.hh" 53#include "cpu/thread_context.hh" 54#include "debug/TLB.hh" 55#include "mem/packet_access.hh" 56#include "mem/page_table.hh" 57#include "mem/request.hh" 58#include "sim/full_system.hh" 59#include "sim/process.hh" 60 61namespace X86ISA { 62 63TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size), 64 lruSeq(0) 65{ 66 if (!size) 67 fatal("TLBs must have a non-zero size.\n"); 68 tlb = new TlbEntry[size]; 69 std::memset(tlb, 0, sizeof(TlbEntry) * size); 70 71 for (int x = 0; x < size; x++) { 72 tlb[x].trieHandle = NULL; 73 freeList.push_back(&tlb[x]); 74 } 75 76 walker = p->walker; 77 walker->setTLB(this); 78} 79 80void 81TLB::evictLRU() 82{ 83 // Find the entry with the lowest (and hence least recently updated) 84 // sequence number. 85 86 unsigned lru = 0; 87 for (unsigned i = 1; i < size; i++) { 88 if (tlb[i].lruSeq < tlb[lru].lruSeq) 89 lru = i; 90 } 91 92 assert(tlb[lru].trieHandle); 93 trie.remove(tlb[lru].trieHandle); 94 tlb[lru].trieHandle = NULL; 95 freeList.push_back(&tlb[lru]); 96} 97 98TlbEntry * 99TLB::insert(Addr vpn, TlbEntry &entry) 100{ 101 // If somebody beat us to it, just use that existing entry. 102 TlbEntry *newEntry = trie.lookup(vpn); 103 if (newEntry) { 104 assert(newEntry->vaddr == vpn); 105 return newEntry; 106 } 107 108 if (freeList.empty()) 109 evictLRU(); 110 111 newEntry = freeList.front(); 112 freeList.pop_front(); 113 114 *newEntry = entry; 115 newEntry->lruSeq = nextSeq(); 116 newEntry->vaddr = vpn; 117 newEntry->trieHandle = 118 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); 119 return newEntry; 120} 121 122TlbEntry * 123TLB::lookup(Addr va, bool update_lru) 124{ 125 TlbEntry *entry = trie.lookup(va); 126 if (entry && update_lru) 127 entry->lruSeq = nextSeq(); 128 return entry; 129} 130 131void 132TLB::flushAll() 133{ 134 DPRINTF(TLB, "Invalidating all entries.\n"); 135 for (unsigned i = 0; i < size; i++) { 136 if (tlb[i].trieHandle) { 137 trie.remove(tlb[i].trieHandle); 138 tlb[i].trieHandle = NULL; 139 freeList.push_back(&tlb[i]); 140 } 141 } 142} 143 144void 145TLB::setConfigAddress(uint32_t addr) 146{ 147 configAddress = addr; 148} 149 150void 151TLB::flushNonGlobal() 152{ 153 DPRINTF(TLB, "Invalidating all non global entries.\n"); 154 for (unsigned i = 0; i < size; i++) { 155 if (tlb[i].trieHandle && !tlb[i].global) { 156 trie.remove(tlb[i].trieHandle); 157 tlb[i].trieHandle = NULL; 158 freeList.push_back(&tlb[i]); 159 } 160 } 161} 162 163void 164TLB::demapPage(Addr va, uint64_t asn) 165{ 166 TlbEntry *entry = trie.lookup(va); 167 if (entry) { 168 trie.remove(entry->trieHandle); 169 entry->trieHandle = NULL; 170 freeList.push_back(entry); 171 } 172} 173 174Fault 175TLB::translateInt(RequestPtr req, ThreadContext *tc) 176{ 177 DPRINTF(TLB, "Addresses references internal memory.\n"); 178 Addr vaddr = req->getVaddr(); 179 Addr prefix = (vaddr >> 3) & IntAddrPrefixMask; 180 if (prefix == IntAddrPrefixCPUID) { 181 panic("CPUID memory space not yet implemented!\n"); 182 } else if (prefix == IntAddrPrefixMSR) { 183 vaddr = (vaddr >> 3) & ~IntAddrPrefixMask; 184 req->setFlags(Request::MMAPPED_IPR); 185 186 MiscRegIndex regNum; 187 if (!msrAddrToIndex(regNum, vaddr)) 188 return new GeneralProtection(0); 189 190 //The index is multiplied by the size of a MiscReg so that 191 //any memory dependence calculations will not see these as 192 //overlapping. 193 req->setPaddr((Addr)regNum * sizeof(MiscReg)); 194 return NoFault; 195 } else if (prefix == IntAddrPrefixIO) { 196 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 197 // bitmap in the TSS. 198 199 Addr IOPort = vaddr & ~IntAddrPrefixMask; 200 // Make sure the address fits in the expected 16 bit IO address 201 // space. 202 assert(!(IOPort & ~0xFFFF)); 203 if (IOPort == 0xCF8 && req->getSize() == 4) { 204 req->setFlags(Request::MMAPPED_IPR); 205 req->setPaddr(MISCREG_PCI_CONFIG_ADDRESS * sizeof(MiscReg)); 206 } else if ((IOPort & ~mask(2)) == 0xCFC) { 207 req->setFlags(Request::UNCACHEABLE); 208 Addr configAddress = 209 tc->readMiscRegNoEffect(MISCREG_PCI_CONFIG_ADDRESS); 210 if (bits(configAddress, 31, 31)) { 211 req->setPaddr(PhysAddrPrefixPciConfig | 212 mbits(configAddress, 30, 2) | 213 (IOPort & mask(2))); 214 } else { 215 req->setPaddr(PhysAddrPrefixIO | IOPort); 216 } 217 } else { 218 req->setFlags(Request::UNCACHEABLE); 219 req->setPaddr(PhysAddrPrefixIO | IOPort); 220 } 221 return NoFault; 222 } else { 223 panic("Access to unrecognized internal address space %#x.\n", 224 prefix); 225 } 226} 227 228Fault 229TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const 230{ 231 Addr paddr = req->getPaddr(); 232 233 // Check for an access to the local APIC 234 if (FullSystem) { 235 LocalApicBase localApicBase = 236 tc->readMiscRegNoEffect(MISCREG_APIC_BASE); 237 AddrRange apicRange(localApicBase.base * PageBytes, 238 (localApicBase.base + 1) * PageBytes - 1); 239 240 if (apicRange.contains(paddr)) { 241 // The Intel developer's manuals say the below restrictions apply, 242 // but the linux kernel, because of a compiler optimization, breaks 243 // them. 244 /* 245 // Check alignment 246 if (paddr & ((32/8) - 1)) 247 return new GeneralProtection(0); 248 // Check access size 249 if (req->getSize() != (32/8)) 250 return new GeneralProtection(0); 251 */ 252 // Force the access to be uncacheable. 253 req->setFlags(Request::UNCACHEABLE); 254 req->setPaddr(x86LocalAPICAddress(tc->contextId(), 255 paddr - apicRange.start())); 256 } 257 } 258 259 return NoFault; 260} 261 262Fault 263TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation, 264 Mode mode, bool &delayedResponse, bool timing) 265{ 266 uint32_t flags = req->getFlags(); 267 int seg = flags & SegmentFlagMask; 268 bool storeCheck = flags & (StoreCheck << FlagShift); 269 270 delayedResponse = false; 271 272 // If this is true, we're dealing with a request to a non-memory address 273 // space. 274 if (seg == SEGMENT_REG_MS) { 275 return translateInt(req, tc); 276 } 277 278 Addr vaddr = req->getVaddr(); 279 DPRINTF(TLB, "Translating vaddr %#x.\n", vaddr); 280 281 HandyM5Reg m5Reg = tc->readMiscRegNoEffect(MISCREG_M5_REG); 282 283 // If protected mode has been enabled... 284 if (m5Reg.prot) { 285 DPRINTF(TLB, "In protected mode.\n"); 286 // If we're not in 64-bit mode, do protection/limit checks 287 if (m5Reg.mode != LongMode) { 288 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 289 // Check for a NULL segment selector. 290 if (!(seg == SEGMENT_REG_TSG || seg == SYS_SEGMENT_REG_IDTR || 291 seg == SEGMENT_REG_HS || seg == SEGMENT_REG_LS) 292 && !tc->readMiscRegNoEffect(MISCREG_SEG_SEL(seg))) 293 return new GeneralProtection(0); 294 bool expandDown = false; 295 SegAttr attr = tc->readMiscRegNoEffect(MISCREG_SEG_ATTR(seg)); 296 if (seg >= SEGMENT_REG_ES && seg <= SEGMENT_REG_HS) { 297 if (!attr.writable && (mode == Write || storeCheck)) 298 return new GeneralProtection(0); 299 if (!attr.readable && mode == Read) 300 return new GeneralProtection(0); 301 expandDown = attr.expandDown; 302 303 } 304 Addr base = tc->readMiscRegNoEffect(MISCREG_SEG_BASE(seg)); 305 Addr limit = tc->readMiscRegNoEffect(MISCREG_SEG_LIMIT(seg)); 306 bool sizeOverride = (flags & (AddrSizeFlagBit << FlagShift)); 307 unsigned logSize = sizeOverride ? (unsigned)m5Reg.altAddr 308 : (unsigned)m5Reg.defAddr; 309 int size = (1 << logSize) * 8; 310 Addr offset = bits(vaddr - base, size - 1, 0); 311 Addr endOffset = offset + req->getSize() - 1; 312 if (expandDown) { 313 DPRINTF(TLB, "Checking an expand down segment.\n"); 314 warn_once("Expand down segments are untested.\n"); 315 if (offset <= limit || endOffset <= limit) 316 return new GeneralProtection(0); 317 } else { 318 if (offset > limit || endOffset > limit) 319 return new GeneralProtection(0); 320 } 321 } 322 if (m5Reg.submode != SixtyFourBitMode || 323 (flags & (AddrSizeFlagBit << FlagShift))) 324 vaddr &= mask(32); 325 // If paging is enabled, do the translation. 326 if (m5Reg.paging) { 327 DPRINTF(TLB, "Paging enabled.\n"); 328 // The vaddr already has the segment base applied. 329 TlbEntry *entry = lookup(vaddr); 330 if (!entry) { 331 if (FullSystem) { 332 Fault fault = walker->start(tc, translation, req, mode); 333 if (timing || fault != NoFault) { 334 // This gets ignored in atomic mode. 335 delayedResponse = true; 336 return fault; 337 } 338 entry = lookup(vaddr); 339 assert(entry); 340 } else { 341 DPRINTF(TLB, "Handling a TLB miss for " 342 "address %#x at pc %#x.\n", 343 vaddr, tc->instAddr()); 344 345 Process *p = tc->getProcessPtr(); 346 TlbEntry newEntry; 347 bool success = p->pTable->lookup(vaddr, newEntry); 348 if (!success && mode != Execute) { 349 // Check if we just need to grow the stack. 350 if (p->fixupStackFault(vaddr)) { 351 // If we did, lookup the entry for the new page. 352 success = p->pTable->lookup(vaddr, newEntry); 353 } 354 } 355 if (!success) { 356 return new PageFault(vaddr, true, mode, true, false); 357 } else { 358 Addr alignedVaddr = p->pTable->pageAlign(vaddr); 359 DPRINTF(TLB, "Mapping %#x to %#x\n", alignedVaddr, 360 newEntry.pageStart()); 361 entry = insert(alignedVaddr, newEntry); 362 } 363 DPRINTF(TLB, "Miss was serviced.\n"); 364 } 365 } 366 367 DPRINTF(TLB, "Entry found with paddr %#x, " 368 "doing protection checks.\n", entry->paddr); 369 // Do paging protection checks. 370 bool inUser = (m5Reg.cpl == 3 && 371 !(flags & (CPL0FlagBit << FlagShift))); 372 CR0 cr0 = tc->readMiscRegNoEffect(MISCREG_CR0); 373 bool badWrite = (!entry->writable && (inUser || cr0.wp)); 374 if ((inUser && !entry->user) || (mode == Write && badWrite)) { 375 // The page must have been present to get into the TLB in 376 // the first place. We'll assume the reserved bits are 377 // fine even though we're not checking them. 378 return new PageFault(vaddr, true, mode, inUser, false); 379 } 380 if (storeCheck && badWrite) { 381 // This would fault if this were a write, so return a page 382 // fault that reflects that happening. 383 return new PageFault(vaddr, true, Write, inUser, false); 384 } 385 386 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); 387 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 388 req->setPaddr(paddr); 389 if (entry->uncacheable) 390 req->setFlags(Request::UNCACHEABLE); 391 } else { 392 //Use the address which already has segmentation applied. 393 DPRINTF(TLB, "Paging disabled.\n"); 394 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 395 req->setPaddr(vaddr); 396 } 397 } else { 398 // Real mode 399 DPRINTF(TLB, "In real mode.\n"); 400 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); 401 req->setPaddr(vaddr); 402 } 403 404 return finalizePhysical(req, tc, mode); 405} 406 407Fault 408TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) 409{ 410 bool delayedResponse; 411 return TLB::translate(req, tc, NULL, mode, delayedResponse, false); 412} 413 414void 415TLB::translateTiming(RequestPtr req, ThreadContext *tc, 416 Translation *translation, Mode mode) 417{ 418 bool delayedResponse; 419 assert(translation); 420 Fault fault = 421 TLB::translate(req, tc, translation, mode, delayedResponse, true); 422 if (!delayedResponse) 423 translation->finish(fault, req, tc, mode); 424} 425 426Fault 427TLB::translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode) 428{ 429 panic("Not implemented\n"); 430 return NoFault; 431} 432 433Walker * 434TLB::getWalker() 435{ 436 return walker; 437} 438 439void 440TLB::serialize(std::ostream &os) 441{
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