1/* 2 * Copyright (c) 2007-2008 The Hewlett-Packard Development Company 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55#include "mem/packet_access.hh" 56#include "mem/page_table.hh" 57#include "mem/request.hh" 58#include "sim/full_system.hh" 59#include "sim/process.hh" 60 61namespace X86ISA { 62 |
63TLB::TLB(const Params *p) : BaseTLB(p), configAddress(0), size(p->size), 64 lruSeq(0) |
65{ |
66 if (!size) 67 fatal("TLBs must have a non-zero size.\n"); |
68 tlb = new TlbEntry[size]; 69 std::memset(tlb, 0, sizeof(TlbEntry) * size); 70 |
71 for (int x = 0; x < size; x++) { 72 tlb[x].trieHandle = NULL; |
73 freeList.push_back(&tlb[x]); |
74 } |
75 76 walker = p->walker; 77 walker->setTLB(this); 78} 79 |
80void 81TLB::evictLRU() 82{ 83 // Find the entry with the lowest (and hence least recently updated) 84 // sequence number. 85 86 unsigned lru = 0; 87 for (unsigned i = 1; i < size; i++) { 88 if (tlb[i].lruSeq < tlb[lru].lruSeq) 89 lru = i; 90 } 91 92 assert(tlb[lru].trieHandle); 93 trie.remove(tlb[lru].trieHandle); 94 tlb[lru].trieHandle = NULL; 95 freeList.push_back(&tlb[lru]); 96} 97 |
98TlbEntry * 99TLB::insert(Addr vpn, TlbEntry &entry) 100{ 101 //TODO Deal with conflicting entries 102 103 TlbEntry *newEntry = NULL; |
104 if (freeList.empty()) 105 evictLRU(); 106 newEntry = freeList.front(); 107 freeList.pop_front(); 108 |
109 *newEntry = entry; |
110 newEntry->lruSeq = nextSeq(); |
111 newEntry->vaddr = vpn; |
112 newEntry->trieHandle = 113 trie.insert(vpn, TlbEntryTrie::MaxBits - entry.logBytes, newEntry); |
114 return newEntry; 115} 116 |
117TlbEntry * 118TLB::lookup(Addr va, bool update_lru) 119{ |
120 TlbEntry *entry = trie.lookup(va); 121 if (entry && update_lru) 122 entry->lruSeq = nextSeq(); 123 return entry; |
124} 125 126void 127TLB::invalidateAll() 128{ 129 DPRINTF(TLB, "Invalidating all entries.\n"); |
130 for (unsigned i = 0; i < size; i++) { 131 if (tlb[i].trieHandle) { 132 trie.remove(tlb[i].trieHandle); 133 tlb[i].trieHandle = NULL; 134 freeList.push_back(&tlb[i]); 135 } |
136 } 137} 138 139void 140TLB::setConfigAddress(uint32_t addr) 141{ 142 configAddress = addr; 143} 144 145void 146TLB::invalidateNonGlobal() 147{ 148 DPRINTF(TLB, "Invalidating all non global entries.\n"); |
149 for (unsigned i = 0; i < size; i++) { 150 if (tlb[i].trieHandle && !tlb[i].global) { 151 trie.remove(tlb[i].trieHandle); 152 tlb[i].trieHandle = NULL; 153 freeList.push_back(&tlb[i]); |
154 } 155 } 156} 157 158void 159TLB::demapPage(Addr va, uint64_t asn) 160{ |
161 TlbEntry *entry = trie.lookup(va); 162 if (entry) { 163 trie.remove(entry->trieHandle); 164 entry->trieHandle = NULL; 165 freeList.push_back(entry); |
166 } 167} 168 169Fault 170TLB::translateInt(RequestPtr req, ThreadContext *tc) 171{ 172 DPRINTF(TLB, "Addresses references internal memory.\n"); 173 Addr vaddr = req->getVaddr(); --- 169 unchanged lines hidden (view full) --- 343 return new PageFault(vaddr, true, mode, inUser, false); 344 } 345 if (storeCheck && badWrite) { 346 // This would fault if this were a write, so return a page 347 // fault that reflects that happening. 348 return new PageFault(vaddr, true, Write, inUser, false); 349 } 350 |
351 Addr paddr = entry->paddr | (vaddr & mask(entry->logBytes)); |
352 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr); 353 req->setPaddr(paddr); 354 if (entry->uncacheable) 355 req->setFlags(Request::UNCACHEABLE); 356 } else { 357 //Use the address which already has segmentation applied. 358 DPRINTF(TLB, "Paging disabled.\n"); 359 DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, vaddr); --- 90 unchanged lines hidden --- |